__adev 65 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h #define mlx5_fpga_dbg(__adev, format, ...) \ __adev 66 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h mlx5_core_dbg((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \ __adev 69 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h #define mlx5_fpga_err(__adev, format, ...) \ __adev 70 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h mlx5_core_err((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \ __adev 73 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h #define mlx5_fpga_warn(__adev, format, ...) \ __adev 74 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h mlx5_core_warn((__adev)->mdev, "FPGA: %s:%d:(pid %d): " format, \ __adev 77 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h #define mlx5_fpga_warn_ratelimited(__adev, format, ...) \ __adev 78 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h mlx5_core_err_rl((__adev)->mdev, "FPGA: %s:%d: " \ __adev 81 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h #define mlx5_fpga_notice(__adev, format, ...) \ __adev 82 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__) __adev 84 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h #define mlx5_fpga_info(__adev, format, ...) \ __adev 85 drivers/net/ethernet/mellanox/mlx5/core/fpga/core.h mlx5_core_info((__adev)->mdev, "FPGA: " format, ##__VA_ARGS__)