__SHIFT 1109 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT __SHIFT 58 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 47 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 49 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 64 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c CLK_MASK_SH_LIST_NV10(__SHIFT) __SHIFT 156 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 178 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 245 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) __SHIFT 267 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT) __SHIFT 304 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c AUD_COMMON_MASK_SH_LIST(__SHIFT) __SHIFT 323 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 335 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c DMCU_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 347 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c ABM_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 458 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c HWSEQ_DCE10_MASK_SH_LIST(__SHIFT) __SHIFT 500 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c MI_DCE8_MASK_SH_LIST(__SHIFT), __SHIFT 630 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 157 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c DMCU_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 169 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ABM_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 188 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 207 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 271 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c SE_COMMON_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 293 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c OPP_COMMON_MASK_SH_LIST_DCE_110(__SHIFT) __SHIFT 331 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c AUD_COMMON_MASK_SH_LIST(__SHIFT) __SHIFT 353 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 504 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c HWSEQ_DCE11_MASK_SH_LIST(__SHIFT), __SHIFT 545 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c MI_DCE11_MASK_SH_LIST(__SHIFT), __SHIFT 676 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 156 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c DMCU_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 168 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ABM_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 190 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 212 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 278 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c SE_COMMON_MASK_SH_LIST_DCE112(__SHIFT) __SHIFT 300 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c OPP_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) __SHIFT 337 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c AUD_COMMON_MASK_SH_LIST(__SHIFT) __SHIFT 359 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) __SHIFT 478 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c HWSEQ_DCE112_MASK_SH_LIST(__SHIFT) __SHIFT 517 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c MI_DCE11_2_MASK_SH_LIST(__SHIFT) __SHIFT 649 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 165 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c DMCU_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 177 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ABM_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 199 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c IPP_DCE120_MASK_SH_LIST_SOC_BASE(__SHIFT) __SHIFT 221 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c XFM_COMMON_MASK_SH_LIST_SOC_BASE(__SHIFT) __SHIFT 289 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c SE_COMMON_MASK_SH_LIST_DCE120(__SHIFT) __SHIFT 311 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c OPP_COMMON_MASK_SH_LIST_DCE_120(__SHIFT) __SHIFT 352 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) __SHIFT 374 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c CS_COMMON_MASK_SH_LIST_DCE_112(__SHIFT) __SHIFT 423 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 712 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c HWSEQ_DCE12_MASK_SH_LIST(__SHIFT) __SHIFT 725 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c HWSEQ_VG20_MASK_SH_LIST(__SHIFT) __SHIFT 786 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c MI_DCE12_MASK_SH_LIST(__SHIFT) __SHIFT 173 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 195 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT) __SHIFT 262 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT) __SHIFT 284 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT) __SHIFT 322 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c AUD_COMMON_MASK_SH_LIST(__SHIFT) __SHIFT 342 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 405 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c DMCU_MASK_SH_LIST_DCE80(__SHIFT) __SHIFT 416 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c ABM_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 510 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT) __SHIFT 570 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c HWSEQ_DCE8_MASK_SH_LIST(__SHIFT) __SHIFT 612 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c MI_DCE8_MASK_SH_LIST(__SHIFT), __SHIFT 213 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c DMCU_MASK_SH_LIST_DCN10(__SHIFT) __SHIFT 225 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ABM_MASK_SH_LIST_DCN10(__SHIFT) __SHIFT 245 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c SE_COMMON_MASK_SH_LIST_DCN10(__SHIFT) __SHIFT 270 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) __SHIFT 315 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c LINK_ENCODER_MASK_SH_LIST_DCN10(__SHIFT) __SHIFT 335 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c IPP_MASK_SH_LIST_DCN10(__SHIFT) __SHIFT 355 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c OPP_MASK_SH_LIST_DCN10(__SHIFT) __SHIFT 390 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c TF_REG_LIST_SH_MASK_DCN10(__SHIFT), __SHIFT 412 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c MPC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) __SHIFT 430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c TG_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) __SHIFT 455 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c HUBP_MASK_SH_LIST_DCN10(__SHIFT) __SHIFT 467 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c HUBBUB_MASK_SH_LIST_DCN10(__SHIFT) __SHIFT 487 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c CS_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) __SHIFT 661 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c I2C_COMMON_MASK_SH_LIST_DCE110(__SHIFT) __SHIFT 830 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c HWSEQ_DCN1_MASK_SH_LIST(__SHIFT) __SHIFT 485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) __SHIFT 497 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DMCU_MASK_SH_LIST_DCN10(__SHIFT) __SHIFT 509 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ABM_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 537 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) __SHIFT 559 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 634 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c IPP_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 656 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c OPP_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 695 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c TF_REG_LIST_SH_MASK_DCN20(__SHIFT) __SHIFT 712 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DWBC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) __SHIFT 729 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) __SHIFT 752 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) __SHIFT 773 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) __SHIFT 795 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c HUBP_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 807 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c HUBBUB_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 839 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DCN20_VMID_MASK_SH_LIST(__SHIFT) __SHIFT 862 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) __SHIFT 875 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DCCG_MASK_SH_LIST_DCN2(__SHIFT) __SHIFT 1052 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) __SHIFT 1238 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c HWSEQ_DCN2_MASK_SH_LIST(__SHIFT) __SHIFT 342 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) __SHIFT 360 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DMCUB_COMMON_MASK_SH_LIST_BASE(__SHIFT) __SHIFT 388 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT) __SHIFT 400 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DCCG_MASK_SH_LIST_DCN2(__SHIFT) __SHIFT 422 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c OPP_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 440 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) __SHIFT 461 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT) __SHIFT 481 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c HUBP_MASK_SH_LIST_DCN21(__SHIFT) __SHIFT 493 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c HUBBUB_MASK_SH_LIST_DCN21(__SHIFT) __SHIFT 526 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DCN20_VMID_MASK_SH_LIST(__SHIFT) __SHIFT 549 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DSC_REG_LIST_SH_MASK_DCN20(__SHIFT) __SHIFT 570 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c IPP_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 612 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c TF_REG_LIST_SH_MASK_DCN20(__SHIFT) __SHIFT 633 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT) __SHIFT 703 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT) __SHIFT 1388 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c HWSEQ_DCN21_MASK_SH_LIST(__SHIFT) __SHIFT 115 drivers/gpu/drm/amd/display/dc/dm_services.h reg_name ## __ ## reg_field ## __SHIFT) __SHIFT 132 drivers/gpu/drm/amd/display/dc/dm_services.h reg_name ## __ ## reg_field ## __SHIFT) __SHIFT 142 drivers/gpu/drm/amd/display/dc/dm_services.h #define FD(reg_field) reg_field ## __SHIFT, \ __SHIFT 177 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) __SHIFT 184 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT) __SHIFT 73 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c HPD_MASK_SH_LIST(__SHIFT) __SHIFT 109 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c DDC_MASK_SH_LIST(__SHIFT) __SHIFT 86 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c HPD_MASK_SH_LIST(__SHIFT) __SHIFT 122 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c DDC_MASK_SH_LIST(__SHIFT) __SHIFT 73 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c HPD_MASK_SH_LIST_DCE8(__SHIFT) __SHIFT 109 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c DDC_MASK_SH_LIST(__SHIFT) __SHIFT 82 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c HPD_MASK_SH_LIST(__SHIFT) __SHIFT 118 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c DDC_MASK_SH_LIST(__SHIFT) __SHIFT 142 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c GENERIC_MASK_SH_LIST(__SHIFT, A), __SHIFT 143 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c GENERIC_MASK_SH_LIST(__SHIFT, B), __SHIFT 93 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c HPD_MASK_SH_LIST(__SHIFT) __SHIFT 125 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), __SHIFT 126 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), __SHIFT 127 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), __SHIFT 128 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), __SHIFT 129 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), __SHIFT 130 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 6) __SHIFT 159 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c GENERIC_MASK_SH_LIST(__SHIFT, A), __SHIFT 160 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c GENERIC_MASK_SH_LIST(__SHIFT, B), __SHIFT 90 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c HPD_MASK_SH_LIST(__SHIFT) __SHIFT 120 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 1), __SHIFT 121 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 2), __SHIFT 122 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 3), __SHIFT 123 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 4), __SHIFT 124 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 5), __SHIFT 125 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(__SHIFT, 6) __SHIFT 153 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c GENERIC_MASK_SH_LIST(__SHIFT, A), __SHIFT 37 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _shift = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## __SHIFT __SHIFT 62 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _shift = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## __SHIFT __SHIFT 79 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _shift = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## __SHIFT __SHIFT 34 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h .type ## _shift = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## __SHIFT __SHIFT 42 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h .type ## _shift = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## __SHIFT __SHIFT 121 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT __SHIFT 124 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT __SHIFT 13 drivers/gpu/drm/etnaviv/etnaviv_cmd_parser.c #define EXTRACT(val, field) (((val) & field##__MASK) >> field##__SHIFT) __SHIFT 172 drivers/gpu/drm/etnaviv/etnaviv_gpu.c (((val) & field##__MASK) >> field##__SHIFT) __SHIFT 443 drivers/gpu/drm/msm/msm_drv.h #define FIELD(val, name) (((val) & name ## __MASK) >> name ## __SHIFT)