_MASK 203 arch/arc/kernel/troubleshoot.c #define STS_BIT(r, bit) r->status32 & STATUS_##bit##_MASK ? #bit" " : "" _MASK 163 arch/arm/include/uapi/asm/kvm.h (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK) _MASK 271 arch/arm/mach-omap2/id.c if (((status & OMAP3_ ##feat## _MASK) \ _MASK 295 arch/arm/mach-pxa/mfp-pxa2xx.c gpio_desc[(gpio)].mux_mask = PWER_ ## mux ## _MASK; \ _MASK 26 arch/arm64/include/asm/image.h (((flags) >> field##_SHIFT) & field##_MASK) _MASK 205 arch/arm64/include/uapi/asm/kvm.h KVM_REG_ARM64_SYSREG_ ## n ## _MASK) _MASK 21 arch/m68k/include/asm/MC68328.h #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) _MASK 22 arch/m68k/include/asm/MC68328.h #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) _MASK 22 arch/m68k/include/asm/MC68EZ328.h #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) _MASK 23 arch/m68k/include/asm/MC68EZ328.h #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) _MASK 24 arch/m68k/include/asm/MC68VZ328.h #define PUT_FIELD(field, val) (((val) << field##_SHIFT) & field##_MASK) _MASK 25 arch/m68k/include/asm/MC68VZ328.h #define GET_FIELD(reg, field) (((reg) & field##_MASK) >> field##_SHIFT) _MASK 343 arch/mips/include/asm/mach-loongson64/loongson.h s##_WIN##w##_MASK = ~(size-1); \ _MASK 25 arch/mips/include/asm/mach-pnx833x/pnx833x.h (((val) & PNX##cpu##_##reg##_##field##_MASK) >> \ _MASK 38 arch/mips/include/asm/mach-pnx833x/pnx833x.h (PNX##cpu##_##reg = (PNX##cpu##_##reg & ~(PNX##cpu##_##reg##_##field##_MASK)) | \ _MASK 410 arch/mips/include/asm/mips-boards/bonito64.h #define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE) (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) _MASK 413 arch/mips/include/asm/mips-boards/bonito64.h #define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG) (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK) _MASK 416 arch/mips/include/asm/mips-boards/bonito64.h #define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT) _MASK 83 arch/xtensa/include/asm/processor.h #define _XTENSA_INTLEVEL_MASK(level) (XCHAL_INTLEVEL##level##_MASK) _MASK 38 drivers/block/drbd/drbd_state.h ({ union drbd_state mask; mask.i = 0; mask.T = T##_MASK; mask; }), \ _MASK 41 drivers/block/drbd/drbd_state.h ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \ _MASK 42 drivers/block/drbd/drbd_state.h mask.T2 = T2##_MASK; mask; }), \ _MASK 46 drivers/block/drbd/drbd_state.h ({ union drbd_state mask; mask.i = 0; mask.T1 = T1##_MASK; \ _MASK 47 drivers/block/drbd/drbd_state.h mask.T2 = T2##_MASK; mask.T3 = T3##_MASK; mask; }), \ _MASK 40 drivers/clk/clk-nspire.c #define EXTRACT(var, prop) (((var)>>prop##_SHIFT) & prop##_MASK) _MASK 1069 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) _MASK 1070 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) _MASK 1110 drivers/gpu/drm/amd/amdgpu/amdgpu.h #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK _MASK 62 drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 51 drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 53 drivers/gpu/drm/amd/display/dc/clk_mgr/dce112/dce112_clk_mgr.c CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 68 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c CLK_MASK_SH_LIST_NV10(_MASK) _MASK 160 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 182 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) _MASK 249 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) _MASK 271 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK) _MASK 308 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c AUD_COMMON_MASK_SH_LIST(_MASK) _MASK 327 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 339 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c DMCU_MASK_SH_LIST_DCE110(_MASK) _MASK 351 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c ABM_MASK_SH_LIST_DCE110(_MASK) _MASK 462 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c HWSEQ_DCE10_MASK_SH_LIST(_MASK) _MASK 505 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c MI_DCE8_MASK_SH_LIST(_MASK), _MASK 634 drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 161 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c DMCU_MASK_SH_LIST_DCE110(_MASK) _MASK 173 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c ABM_MASK_SH_LIST_DCE110(_MASK) _MASK 192 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 211 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) _MASK 275 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c SE_COMMON_MASK_SH_LIST_DCE110(_MASK) _MASK 297 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c OPP_COMMON_MASK_SH_LIST_DCE_110(_MASK) _MASK 335 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c AUD_COMMON_MASK_SH_LIST(_MASK) _MASK 357 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 508 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c HWSEQ_DCE11_MASK_SH_LIST(_MASK), _MASK 550 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c MI_DCE11_MASK_SH_LIST(_MASK), _MASK 680 drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) _MASK 160 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c DMCU_MASK_SH_LIST_DCE110(_MASK) _MASK 172 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c ABM_MASK_SH_LIST_DCE110(_MASK) _MASK 194 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 216 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c XFM_COMMON_MASK_SH_LIST_DCE110(_MASK) _MASK 282 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c SE_COMMON_MASK_SH_LIST_DCE112(_MASK) _MASK 304 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c OPP_COMMON_MASK_SH_LIST_DCE_112(_MASK) _MASK 341 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c AUD_COMMON_MASK_SH_LIST(_MASK) _MASK 363 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) _MASK 482 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c HWSEQ_DCE112_MASK_SH_LIST(_MASK) _MASK 521 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c MI_DCE11_2_MASK_SH_LIST(_MASK) _MASK 653 drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) _MASK 169 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c DMCU_MASK_SH_LIST_DCE110(_MASK) _MASK 181 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c ABM_MASK_SH_LIST_DCE110(_MASK) _MASK 203 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c IPP_DCE120_MASK_SH_LIST_SOC_BASE(_MASK) _MASK 225 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c XFM_COMMON_MASK_SH_LIST_SOC_BASE(_MASK) _MASK 293 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c SE_COMMON_MASK_SH_LIST_DCE120(_MASK) _MASK 315 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c OPP_COMMON_MASK_SH_LIST_DCE_120(_MASK) _MASK 356 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) _MASK 378 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c CS_COMMON_MASK_SH_LIST_DCE_112(_MASK) _MASK 427 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) _MASK 716 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c HWSEQ_DCE12_MASK_SH_LIST(_MASK) _MASK 729 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c HWSEQ_VG20_MASK_SH_LIST(_MASK) _MASK 790 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c MI_DCE12_MASK_SH_LIST(_MASK) _MASK 177 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 199 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c XFM_COMMON_MASK_SH_LIST_DCE80(_MASK) _MASK 266 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK) _MASK 288 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK) _MASK 326 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c AUD_COMMON_MASK_SH_LIST(_MASK) _MASK 346 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 409 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c DMCU_MASK_SH_LIST_DCE80(_MASK) _MASK 420 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c ABM_MASK_SH_LIST_DCE110(_MASK) _MASK 514 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK) _MASK 574 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c HWSEQ_DCE8_MASK_SH_LIST(_MASK) _MASK 617 drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c MI_DCE8_MASK_SH_LIST(_MASK), _MASK 217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c DMCU_MASK_SH_LIST_DCN10(_MASK) _MASK 229 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c ABM_MASK_SH_LIST_DCN10(_MASK) _MASK 249 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c SE_COMMON_MASK_SH_LIST_DCN10(_MASK) _MASK 274 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) _MASK 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c LINK_ENCODER_MASK_SH_LIST_DCN10(_MASK) _MASK 339 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c IPP_MASK_SH_LIST_DCN10(_MASK), _MASK 359 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c OPP_MASK_SH_LIST_DCN10(_MASK), _MASK 396 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c TF_REG_LIST_SH_MASK_DCN10(_MASK), _MASK 416 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c MPC_COMMON_MASK_SH_LIST_DCN1_0(_MASK), _MASK 434 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c TG_COMMON_MASK_SH_LIST_DCN1_0(_MASK) _MASK 459 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c HUBP_MASK_SH_LIST_DCN10(_MASK) _MASK 471 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c HUBBUB_MASK_SH_LIST_DCN10(_MASK) _MASK 491 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c CS_COMMON_MASK_SH_LIST_DCN1_0(_MASK) _MASK 665 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c I2C_COMMON_MASK_SH_LIST_DCE110(_MASK) _MASK 834 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c HWSEQ_DCN1_MASK_SH_LIST(_MASK) _MASK 489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) _MASK 501 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DMCU_MASK_SH_LIST_DCN10(_MASK) _MASK 513 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c ABM_MASK_SH_LIST_DCN20(_MASK) _MASK 541 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) _MASK 563 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c SE_COMMON_MASK_SH_LIST_DCN20(_MASK) _MASK 616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK) _MASK 638 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c IPP_MASK_SH_LIST_DCN20(_MASK), _MASK 660 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c OPP_MASK_SH_LIST_DCN20(_MASK) _MASK 699 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c TF_REG_LIST_SH_MASK_DCN20(_MASK) _MASK 716 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DWBC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) _MASK 733 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(_MASK) _MASK 756 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) _MASK 777 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) _MASK 799 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c HUBP_MASK_SH_LIST_DCN20(_MASK) _MASK 811 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c HUBBUB_MASK_SH_LIST_DCN20(_MASK) _MASK 843 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DCN20_VMID_MASK_SH_LIST(_MASK) _MASK 866 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DSC_REG_LIST_SH_MASK_DCN20(_MASK) _MASK 879 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c DCCG_MASK_SH_LIST_DCN2(_MASK) _MASK 1056 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) _MASK 1242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c HWSEQ_DCN2_MASK_SH_LIST(_MASK) _MASK 346 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK) _MASK 364 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DMCUB_COMMON_MASK_SH_LIST_BASE(_MASK) _MASK 392 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DCE120_AUD_COMMON_MASK_SH_LIST(_MASK) _MASK 404 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DCCG_MASK_SH_LIST_DCN2(_MASK) _MASK 426 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c OPP_MASK_SH_LIST_DCN20(_MASK) _MASK 444 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK) _MASK 465 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK) _MASK 485 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c HUBP_MASK_SH_LIST_DCN21(_MASK) _MASK 497 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c HUBBUB_MASK_SH_LIST_DCN21(_MASK) _MASK 530 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DCN20_VMID_MASK_SH_LIST(_MASK) _MASK 553 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c DSC_REG_LIST_SH_MASK_DCN20(_MASK) _MASK 574 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c IPP_MASK_SH_LIST_DCN20(_MASK), _MASK 616 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c TF_REG_LIST_SH_MASK_DCN20(_MASK) _MASK 637 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c SE_COMMON_MASK_SH_LIST_DCN20(_MASK) _MASK 707 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c I2C_COMMON_MASK_SH_LIST_DCN2(_MASK) _MASK 1392 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c HWSEQ_DCN21_MASK_SH_LIST(_MASK) _MASK 114 drivers/gpu/drm/amd/display/dc/dm_services.h reg_name ## __ ## reg_field ## _MASK,\ _MASK 131 drivers/gpu/drm/amd/display/dc/dm_services.h reg_name ## __ ## reg_field ## _MASK,\ _MASK 143 drivers/gpu/drm/amd/display/dc/dm_services.h reg_field ## _MASK _MASK 176 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ _MASK 183 drivers/gpu/drm/amd/display/dc/dm_services.h block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\ _MASK 77 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c HPD_MASK_SH_LIST(_MASK) _MASK 113 drivers/gpu/drm/amd/display/dc/gpio/dce110/hw_factory_dce110.c DDC_MASK_SH_LIST(_MASK) _MASK 90 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c HPD_MASK_SH_LIST(_MASK) _MASK 126 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c DDC_MASK_SH_LIST(_MASK) _MASK 77 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c HPD_MASK_SH_LIST_DCE8(_MASK) _MASK 113 drivers/gpu/drm/amd/display/dc/gpio/dce80/hw_factory_dce80.c DDC_MASK_SH_LIST(_MASK) _MASK 86 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c HPD_MASK_SH_LIST(_MASK) _MASK 122 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c DDC_MASK_SH_LIST(_MASK) _MASK 147 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c GENERIC_MASK_SH_LIST(_MASK, A), _MASK 148 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c GENERIC_MASK_SH_LIST(_MASK, B), _MASK 97 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c HPD_MASK_SH_LIST(_MASK) _MASK 134 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(_MASK, 1), _MASK 135 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(_MASK, 2), _MASK 136 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(_MASK, 3), _MASK 137 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(_MASK, 4), _MASK 138 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(_MASK, 5), _MASK 139 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c DDC_MASK_SH_LIST_DCN2(_MASK, 6) _MASK 164 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c GENERIC_MASK_SH_LIST(_MASK, A), _MASK 165 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c GENERIC_MASK_SH_LIST(_MASK, B), _MASK 94 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c HPD_MASK_SH_LIST(_MASK) _MASK 129 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(_MASK, 1), _MASK 130 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(_MASK, 2), _MASK 131 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(_MASK, 3), _MASK 132 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(_MASK, 4), _MASK 133 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(_MASK, 5), _MASK 134 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c DDC_MASK_SH_LIST_DCN2(_MASK, 6) _MASK 157 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c GENERIC_MASK_SH_LIST(_MASK, A), _MASK 36 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _mask = DC_GPIO_DDC ## id ## _ ## type ## __DC_GPIO_DDC ## id ## cd ## _ ## type ## _MASK,\ _MASK 61 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _mask = DC_GPIO_DDCVGA_ ## type ## __DC_GPIO_DDCVGA ## cd ## _ ## type ## _MASK,\ _MASK 78 drivers/gpu/drm/amd/display/dc/gpio/ddc_regs.h .type ## _mask = DC_GPIO_I2CPAD_ ## type ## __DC_GPIO_ ## cd ## _ ## type ## _MASK,\ _MASK 33 drivers/gpu/drm/amd/display/dc/gpio/generic_regs.h .type ## _mask = DC_GPIO_GENERIC_ ## type ## __DC_GPIO_GENERIC ## id ## _ ## type ## _MASK,\ _MASK 41 drivers/gpu/drm/amd/display/dc/gpio/hpd_regs.h .type ## _mask = DC_GPIO_HPD_ ## type ## __DC_GPIO_HPD ## id ## _ ## type ## _MASK,\ _MASK 108 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ _MASK 110 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ _MASK 111 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ _MASK 115 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ _MASK 117 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ _MASK 189 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ _MASK 191 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ _MASK 192 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ _MASK 196 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ _MASK 198 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ _MASK 191 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ _MASK 193 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ _MASK 194 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ _MASK 198 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ _MASK 200 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ _MASK 187 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ _MASK 189 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ _MASK 190 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ _MASK 194 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ _MASK 196 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ _MASK 122 drivers/gpu/drm/amd/include/cgs_common.h #define CGS_REG_FIELD_MASK(reg, field) reg##__##field##_MASK _MASK 125 drivers/gpu/drm/amd/powerplay/hwmgr/smu_helper.h #define PHM_FIELD_MASK(reg, field) reg##__##field##_MASK _MASK 1280 drivers/gpu/drm/gma500/psb_intel_reg.h #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) _MASK 1281 drivers/gpu/drm/gma500/psb_intel_reg.h #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) _MASK 190 drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_regs.h #define HIBMC_FIELD(field, value) (field(value) & field##_MASK) _MASK 529 drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h (((m) & INTEL_GUC_MSG_ ## T ## _MASK) >> INTEL_GUC_MSG_ ## T ## _SHIFT) _MASK 368 drivers/gpu/drm/i915/intel_pm.c (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) _MASK 5880 drivers/gpu/drm/i915/intel_pm.c (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) _MASK 2518 drivers/gpu/drm/radeon/radeon.h #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) _MASK 2519 drivers/gpu/drm/radeon/radeon.h #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) _MASK 14 drivers/gpu/drm/v3d/v3d_regs.h WARN_ON((fieldval & ~field##_MASK) != 0); \ _MASK 15 drivers/gpu/drm/v3d/v3d_regs.h fieldval & field##_MASK; \ _MASK 18 drivers/gpu/drm/v3d/v3d_regs.h #define V3D_GET_FIELD(word, field) (((word) & field##_MASK) >> \ _MASK 211 drivers/gpu/drm/vc4/vc4_qpu_defines.h ((uint32_t)(((word) & field ## _MASK) >> field ## _SHIFT)) _MASK 16 drivers/gpu/drm/vc4/vc4_regs.h WARN_ON((fieldval & ~field##_MASK) != 0); \ _MASK 17 drivers/gpu/drm/vc4/vc4_regs.h fieldval & field##_MASK; \ _MASK 20 drivers/gpu/drm/vc4/vc4_regs.h #define VC4_GET_FIELD(word, field) (((word) & field##_MASK) >> \ _MASK 189 drivers/hwmon/adt7462.c (((value) & prefix##_MASK) >> prefix##_SHIFT) _MASK 1112 drivers/infiniband/hw/hfi1/chip.c { reg##_STATUS, reg##_CLEAR, reg##_MASK, \ _MASK 61 drivers/infiniband/hw/hfi1/exp_rcv.h (((tid) >> EXP_TID_TID##field##_SHIFT) & EXP_TID_TID##field##_MASK) _MASK 64 drivers/infiniband/hw/hfi1/exp_rcv.h (((value) & EXP_TID_TID##field##_MASK) << \ _MASK 67 drivers/infiniband/hw/hfi1/exp_rcv.h (tid) &= ~(EXP_TID_TID##field##_MASK << \ _MASK 101 drivers/infiniband/hw/hfi1/exp_rcv.h (((le32_to_cpu((val))) >> KDETH_##field##_SHIFT) & KDETH_##field##_MASK) _MASK 104 drivers/infiniband/hw/hfi1/exp_rcv.h dwval &= ~(KDETH_##field##_MASK << KDETH_##field##_SHIFT); \ _MASK 105 drivers/infiniband/hw/hfi1/exp_rcv.h dwval |= (((val) & KDETH_##field##_MASK) << \ _MASK 168 drivers/infiniband/hw/hfi1/file_ops.c (((val) & HFI1_MMAP_##field##_MASK) << HFI1_MMAP_##field##_SHIFT) _MASK 170 drivers/infiniband/hw/hfi1/file_ops.c (((token) >> HFI1_MMAP_##field##_SHIFT) & HFI1_MMAP_##field##_MASK) _MASK 88 drivers/infiniband/hw/i40iw/i40iw_d.h #define LS_64(val, field) (((u64)val << field ## _SHIFT) & (field ## _MASK)) _MASK 90 drivers/infiniband/hw/i40iw/i40iw_d.h #define RS_64(val, field) ((u64)(val & field ## _MASK) >> field ## _SHIFT) _MASK 91 drivers/infiniband/hw/i40iw/i40iw_d.h #define LS_32(val, field) ((val << field ## _SHIFT) & (field ## _MASK)) _MASK 92 drivers/infiniband/hw/i40iw/i40iw_d.h #define RS_32(val, field) ((val & field ## _MASK) >> field ## _SHIFT) _MASK 24 drivers/iommu/msm_iommu_hw-8xxx.h #define GET_GLOBAL_FIELD(b, r, F) GET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT) _MASK 26 drivers/iommu/msm_iommu_hw-8xxx.h GET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT) _MASK 29 drivers/iommu/msm_iommu_hw-8xxx.h SET_FIELD(((b) + (r)), F##_MASK, F##_SHIFT, (v)) _MASK 31 drivers/iommu/msm_iommu_hw-8xxx.h SET_FIELD(((b) + (r) + ((c) << CTX_SHIFT)), F##_MASK, F##_SHIFT, (v)) _MASK 835 drivers/media/platform/ti-vpe/cal.c (CAL_CSI2_VC_IRQENABLE_ ##ff ##_IRQ_##vc ##_MASK)) _MASK 145 drivers/media/radio/radio-gemtek.c ((dev)->bu2614data & ~field##_MASK) | ((data) << field##_SHIFT)) _MASK 1050 drivers/misc/habanalabs/habanalabs.h #define REG_FIELD_MASK(reg, field) reg##_##field##_MASK _MASK 457 drivers/net/ethernet/atheros/alx/hw.h (((_data) >> _field ## _SHIFT) & _field ## _MASK) _MASK 460 drivers/net/ethernet/atheros/alx/hw.h (_data) &= ~(_field ## _MASK << _field ## _SHIFT); \ _MASK 461 drivers/net/ethernet/atheros/alx/hw.h (_data) |= ((_value) & _field ## _MASK) << _field ## _SHIFT;\ _MASK 15 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define FIELD_GETX(_x, _name) ((_x) >> (_name##_SHIFT) & (_name##_MASK)) _MASK 17 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h (((_x) & ~((_name##_MASK) << (_name##_SHIFT))) |\ _MASK 18 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h (((_v) & (_name##_MASK)) << (_name##_SHIFT))) _MASK 19 drivers/net/ethernet/atheros/atl1c/atl1c_hw.h #define FIELDX(_name, _v) (((_v) & (_name##_MASK)) << (_name##_SHIFT)) _MASK 2501 drivers/net/ethernet/broadcom/bnx2x/bnx2x.h (((value) & (fname##_MASK)) >> (fname##_SHIFT)) _MASK 20 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h (((u32)(val) & HINIC_API_CMD_PI_##member##_MASK) << \ _MASK 24 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((val) & (~(HINIC_API_CMD_PI_##member##_MASK \ _MASK 32 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h (((u32)(val) & HINIC_API_CMD_CHAIN_REQ_##member##_MASK) << \ _MASK 37 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h HINIC_API_CMD_CHAIN_REQ_##member##_MASK) _MASK 40 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((val) & (~(HINIC_API_CMD_CHAIN_REQ_##member##_MASK \ _MASK 58 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h (((u32)(val) & HINIC_API_CMD_CHAIN_CTRL_##member##_MASK) << \ _MASK 62 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((val) & (~(HINIC_API_CMD_CHAIN_CTRL_##member##_MASK \ _MASK 76 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((((u64)val) & HINIC_API_CMD_CELL_CTRL_##member##_MASK) << \ _MASK 94 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h ((((u64)val) & HINIC_API_CMD_DESC_##member##_MASK) << \ _MASK 103 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h HINIC_API_CMD_STATUS_HEADER_##member##_MASK) _MASK 113 drivers/net/ethernet/huawei/hinic/hinic_hw_api_cmd.h HINIC_API_CMD_STATUS_##member##_MASK) _MASK 40 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c & CMDQ_CEQE_##member##_MASK) _MASK 48 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.c & CMDQ_WQE_ERRCODE_##member##_MASK) _MASK 31 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h (((u64)(val) & HINIC_CMDQ_CTXT_##member##_MASK) \ _MASK 35 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h ((val) & (~((u64)HINIC_CMDQ_CTXT_##member##_MASK \ _MASK 45 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h (((u64)(val) & HINIC_CMDQ_CTXT_##member##_MASK) \ _MASK 49 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h ((val) & (~((u64)HINIC_CMDQ_CTXT_##member##_MASK \ _MASK 57 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h (((u32)(val) & HINIC_SAVED_DATA_##member##_MASK) \ _MASK 62 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h & HINIC_SAVED_DATA_##member##_MASK) _MASK 65 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h ((val) & (~(HINIC_SAVED_DATA_##member##_MASK \ _MASK 79 drivers/net/ethernet/huawei/hinic/hinic_hw_cmdq.h (((u32)(val) & HINIC_CMDQ_DB_INFO_##member##_MASK) \ _MASK 30 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_AEQ_CTRL_0_##member##_MASK) << \ _MASK 34 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_AEQ_CTRL_0_##member##_MASK \ _MASK 46 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_AEQ_CTRL_1_##member##_MASK) << \ _MASK 50 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_AEQ_CTRL_1_##member##_MASK \ _MASK 66 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_CEQ_CTRL_0_##member##_MASK) << \ _MASK 70 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_CEQ_CTRL_0_##member##_MASK \ _MASK 80 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_CEQ_CTRL_1_##member##_MASK) << \ _MASK 84 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_CEQ_CTRL_1_##member##_MASK \ _MASK 98 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_EQ_ELEM_DESC_##member##_MASK) << \ _MASK 103 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h HINIC_EQ_ELEM_DESC_##member##_MASK) _MASK 116 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h (((u32)(val) & HINIC_EQ_CI_##member##_MASK) << \ _MASK 120 drivers/net/ethernet/huawei/hinic/hinic_hw_eqs.h ((val) & (~(HINIC_EQ_CI_##member##_MASK \ _MASK 28 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_DMA_ATTR_##member##_MASK) << \ _MASK 32 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((val) & (~(HINIC_DMA_ATTR_##member##_MASK \ _MASK 47 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((val) >> HINIC_FA0_##member##_SHIFT) & HINIC_FA0_##member##_MASK) _MASK 65 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((val) >> HINIC_FA1_##member##_SHIFT) & HINIC_FA1_##member##_MASK) _MASK 74 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((val) >> HINIC_FA4_##member##_SHIFT) & HINIC_FA4_##member##_MASK) _MASK 77 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((((u32)val) & HINIC_FA4_##member##_MASK) << HINIC_FA4_##member##_SHIFT) _MASK 80 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((val) & (~(HINIC_FA4_##member##_MASK << HINIC_FA4_##member##_SHIFT))) _MASK 86 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_FA5_##member##_MASK) << HINIC_FA5_##member##_SHIFT) _MASK 89 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((val) & (~(HINIC_FA5_##member##_MASK << HINIC_FA5_##member##_SHIFT))) _MASK 95 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_PPF_ELECTION_##member##_MASK) << \ _MASK 100 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h HINIC_PPF_ELECTION_##member##_MASK) _MASK 103 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h ((val) & (~(HINIC_PPF_ELECTION_##member##_MASK \ _MASK 119 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_MSIX_##member##_MASK) << \ _MASK 124 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h HINIC_MSIX_##member##_MASK) _MASK 131 drivers/net/ethernet/huawei/hinic/hinic_hw_if.h (((u32)(val) & HINIC_MSIX_CNT_##member##_MASK) << \ _MASK 47 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h ((u64)((val) & HINIC_MSG_HEADER_##member##_MASK) << \ _MASK 52 drivers/net/ethernet/huawei/hinic/hinic_hw_mgmt.h HINIC_MSG_HEADER_##member##_MASK) _MASK 35 drivers/net/ethernet/huawei/hinic/hinic_hw_qp.h (((u32)(val) & HINIC_SQ_DB_INFO_##member##_MASK) \ _MASK 21 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_CEQ_ATTR_##member##_MASK) \ _MASK 31 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_CI_##member##_MASK) \ _MASK 41 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_WQ_PAGE_##member##_MASK) \ _MASK 59 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_PREF_##member##_MASK) \ _MASK 67 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_SQ_CTXT_WQ_BLOCK_##member##_MASK) \ _MASK 77 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_CEQ_ATTR_##member##_MASK) \ _MASK 87 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_PI_##member##_MASK) << \ _MASK 97 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_WQ_PAGE_##member##_MASK) << \ _MASK 115 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_PREF_##member##_MASK) << \ _MASK 123 drivers/net/ethernet/huawei/hinic/hinic_hw_qp_ctxt.h (((u32)(val) & HINIC_RQ_CTXT_WQ_BLOCK_##member##_MASK) << \ _MASK 25 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_CMDQ_CTRL_##member##_MASK) \ _MASK 30 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h & HINIC_CMDQ_CTRL_##member##_MASK) _MASK 49 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_CMDQ_WQE_HEADER_##member##_MASK) \ _MASK 54 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h & HINIC_CMDQ_WQE_HEADER_##member##_MASK) _MASK 85 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_CTRL_##member##_MASK) \ _MASK 90 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h & HINIC_SQ_CTRL_##member##_MASK) _MASK 93 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h ((u32)(val) & (~(HINIC_SQ_CTRL_##member##_MASK \ _MASK 115 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_TASK_INFO0_##member##_MASK) << \ _MASK 129 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_TASK_INFO1_##member##_MASK) << \ _MASK 147 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_TASK_INFO2_##member##_MASK) << \ _MASK 157 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_SQ_TASK_INFO4_##member##_MASK) << \ _MASK 170 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h HINIC_RQ_CQE_STATUS_##member##_MASK) _MASK 173 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h ((val) & (~(HINIC_RQ_CQE_STATUS_##member##_MASK << \ _MASK 182 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h HINIC_RQ_CQE_SGE_##member##_MASK) _MASK 195 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h (((u32)(val) & HINIC_RQ_CTRL_##member##_MASK) << \ _MASK 218 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h RQ_CQE_STATUS_##member##_MASK) _MASK 230 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h RQ_CQE_OFFOLAD_TYPE_##member##_MASK) _MASK 243 drivers/net/ethernet/huawei/hinic/hinic_hw_wqe.h RQ_CQE_SGE_##member##_MASK) _MASK 100 drivers/net/ethernet/qlogic/qed/qed.h (((name) & (field ## _MASK)) >> (field ## _SHIFT)) _MASK 104 drivers/net/ethernet/qlogic/qed/qed.h (name) &= ~(field ## _MASK); \ _MASK 105 drivers/net/ethernet/qlogic/qed/qed.h (name) |= (((value) << (field ## _SHIFT)) & (field ## _MASK));\ _MASK 2558 drivers/net/ethernet/sun/cassini.h #define CAS_BASE(x, y) (((y) << (x ## _SHIFT)) & (x ## _MASK)) _MASK 2559 drivers/net/ethernet/sun/cassini.h #define CAS_VAL(x, y) (((y) & (x ## _MASK)) >> (x ## _SHIFT)) _MASK 31 drivers/net/wireless/ath/ath10k/core.h #define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB) _MASK 32 drivers/net/wireless/ath/ath10k/core.h #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) _MASK 238 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c BRCMF_SKB_IF_FLAGS_ ## field ## _MASK, \ _MASK 242 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c BRCMF_SKB_IF_FLAGS_ ## field ## _MASK, \ _MASK 273 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c BRCMF_SKB_HTOD_TAG_ ## field ## _MASK, \ _MASK 277 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c BRCMF_SKB_HTOD_TAG_ ## field ## _MASK, \ _MASK 289 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c BRCMF_SKB_HTOD_SEQ_ ## field ## _MASK, \ _MASK 293 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c BRCMF_SKB_HTOD_SEQ_ ## field ## _MASK, \ _MASK 308 drivers/net/wireless/broadcom/brcm80211/brcmfmac/fwsignal.c brcmu_maskget32(txs, BRCMF_FWS_TXSTAT_ ## field ## _MASK, \ _MASK 950 drivers/ntb/hw/idt/ntb_hw_idt.h (((u32)(data) & IDT_ ##field## _MASK) >> IDT_ ##field## _FLD) _MASK 952 drivers/ntb/hw/idt/ntb_hw_idt.h (((u32)(data) & ~IDT_ ##field## _MASK) | \ _MASK 955 drivers/ntb/hw/idt/ntb_hw_idt.h (((u32)(data) & IDT_ ##field## _MASK) == IDT_ ##field## _ ##value) _MASK 52 drivers/nvmem/vf610-ocotp.c #define BF(value, field) (((value) << field) & field##_MASK) _MASK 132 drivers/phy/broadcom/phy-brcm-usb-init.c USB_CTRL_##reg##_##field##_MASK _MASK 145 drivers/phy/broadcom/phy-brcm-usb-init.c USB_CTRL_##reg##_##field##_MASK) _MASK 148 drivers/phy/broadcom/phy-brcm-usb-init.c USB_CTRL_##reg##_##field##_MASK) _MASK 965 drivers/pinctrl/bcm/pinctrl-bcm281xx.c (BCM281XX_ ## type ## _PIN_REG_ ## param ## _MASK) _MASK 127 drivers/pinctrl/pinctrl-st.c & ST_PINCONF_ ##param ##_MASK) _MASK 130 drivers/pinctrl/pinctrl-st.c ((val & ST_PINCONF_ ##param ##_MASK) << \ _MASK 335 drivers/power/supply/bq24190_charger.c .mask = BQ24190_REG_##r##_##f##_MASK, \ _MASK 100 drivers/regulator/da9063-regulator.c .desc.vsel_mask = DA9063_V##regl_name##_MASK, \ _MASK 158 drivers/regulator/max77693-regulator.c .vsel_mask = SAFEOUT_CTRL_SAFEOUT##_num##_MASK, \ _MASK 160 drivers/regulator/max77693-regulator.c .enable_mask = SAFEOUT_CTRL_ENSAFEOUT##_num##_MASK , \ _MASK 201 drivers/regulator/max77693-regulator.c .vsel_mask = MAX77843_REG_SAFEOUTCTRL_SAFEOUT ## num ## _MASK, \ _MASK 177 drivers/regulator/pv88090-regulator.c .vsel_mask = PV88090_V##regl_name##_MASK, \ _MASK 203 drivers/regulator/pv88090-regulator.c .vsel_mask = PV88090_V##regl_name##_MASK, \ _MASK 179 drivers/scsi/isci/registers.h (((value) << name ## _SHIFT) & (name ## _MASK)) _MASK 175 drivers/scsi/lpfc/lpfc_bsg.h ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) _MASK 177 drivers/scsi/lpfc/lpfc_bsg.h (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) _MASK 180 drivers/scsi/lpfc/lpfc_bsg.h name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ _MASK 181 drivers/scsi/lpfc/lpfc_bsg.h ~(name##_MASK << name##_SHIFT))))) _MASK 183 drivers/scsi/lpfc/lpfc_bsg.h ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ _MASK 184 drivers/scsi/lpfc/lpfc_bsg.h ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) _MASK 47 drivers/scsi/lpfc/lpfc_hw4.h ((be32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) _MASK 49 drivers/scsi/lpfc/lpfc_hw4.h ((le32_to_cpu((ptr)->name##_WORD) >> name##_SHIFT) & name##_MASK) _MASK 51 drivers/scsi/lpfc/lpfc_hw4.h (((ptr)->name##_WORD >> name##_SHIFT) & name##_MASK) _MASK 54 drivers/scsi/lpfc/lpfc_hw4.h name##_MASK) << name##_SHIFT) | (le32_to_cpu((ptr)->name##_WORD) & \ _MASK 55 drivers/scsi/lpfc/lpfc_hw4.h ~(name##_MASK << name##_SHIFT))))) _MASK 57 drivers/scsi/lpfc/lpfc_hw4.h ((ptr)->name##_WORD = ((((value) & name##_MASK) << name##_SHIFT) | \ _MASK 58 drivers/scsi/lpfc/lpfc_hw4.h ((ptr)->name##_WORD & ~(name##_MASK << name##_SHIFT)))) _MASK 31 drivers/scsi/qedi/qedi.h (((value) & (name ## _MASK)) >> (name ## _OFFSET)) _MASK 43 drivers/staging/most/net/net.c (((value) >> bitset_name##_SHIFT) & bitset_name##_MASK) _MASK 629 drivers/usb/gadget/udc/amd5536udc.h (((u32Val) & (((u32) ~((u32) bitfield_stub_name##_MASK)))) \ _MASK 631 drivers/usb/gadget/udc/amd5536udc.h & ((u32) bitfield_stub_name##_MASK))) _MASK 640 drivers/usb/gadget/udc/amd5536udc.h & ((u32) bitfield_stub_name##_MASK))) _MASK 644 drivers/usb/gadget/udc/amd5536udc.h ((u32Val & ((u32) bitfield_stub_name##_MASK)) \ _MASK 1166 include/linux/qed/qed_if.h ((_value) &= (_name ## _MASK)) _MASK 1169 include/linux/qed/qed_if.h ((_value & _name ## _MASK) << _name ## _SHIFT) _MASK 1173 include/linux/qed/qed_if.h (value) &= ~(name ## _MASK << name ## _SHIFT); \ _MASK 1178 include/linux/qed/qed_if.h (((value) >> (name ## _SHIFT)) & name ## _MASK) _MASK 351 include/uapi/drm/amdgpu_drm.h (((__u64)(value) & AMDGPU_TILING_##field##_MASK) << AMDGPU_TILING_##field##_SHIFT) _MASK 353 include/uapi/drm/amdgpu_drm.h (((__u64)(value) >> AMDGPU_TILING_##field##_SHIFT) & AMDGPU_TILING_##field##_MASK) _MASK 596 net/mac80211/debugfs_sta.c u8 msk = IEEE80211_HE_##t##_CAP##i##_##n##_MASK; \ _MASK 163 tools/arch/arm/include/uapi/asm/kvm.h (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK) _MASK 205 tools/arch/arm64/include/uapi/asm/kvm.h KVM_REG_ARM64_SYSREG_ ## n ## _MASK) _MASK 149 tools/perf/util/parse-events.c ((config & PERF_EVENT_##name##_MASK) >> PERF_EVENT_##name##_SHIFT) _MASK 869 virt/kvm/arm/vgic/vgic-mmio-v3.c ((((reg) & ICC_SGI1R_AFFINITY_## level ##_MASK) \ _MASK 32 virt/kvm/arm/vgic/vgic.h ((((reg) & VGIC_AFFINITY_## level ##_MASK) \