_HWIP              63 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 			((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 	\
_HWIP              75 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 			((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) 	\
_HWIP              85 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h 		addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg);		\
_HWIP              63 drivers/gpu/drm/amd/amdgpu/soc15.h #define SOC15_REG_ENTRY(ip, inst, reg)	ip##_HWIP, inst, reg##_BASE_IDX, reg
_HWIP              68 drivers/gpu/drm/amd/amdgpu/soc15.h 	{ ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask }
_HWIP              28 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define SOC15_REG_OFFSET(ip, inst, reg)	(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
_HWIP              31 drivers/gpu/drm/amd/amdgpu/soc15_common.h 	WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg,	\
_HWIP              32 drivers/gpu/drm/amd/amdgpu/soc15_common.h 	(RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg)	\
_HWIP              36 drivers/gpu/drm/amd/amdgpu/soc15_common.h 	RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
_HWIP              39 drivers/gpu/drm/amd/amdgpu/soc15_common.h 	RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
_HWIP              42 drivers/gpu/drm/amd/amdgpu/soc15_common.h 	WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
_HWIP              45 drivers/gpu/drm/amd/amdgpu/soc15_common.h 	WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
_HWIP              48 drivers/gpu/drm/amd/amdgpu/soc15_common.h 	WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
_HWIP              53 drivers/gpu/drm/amd/amdgpu/soc15_common.h 		uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
_HWIP              62 drivers/gpu/drm/amd/amdgpu/soc15_common.h 			tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
_HWIP             100 drivers/gpu/drm/amd/amdgpu/soc15_common.h 		uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\
_HWIP             123 drivers/gpu/drm/amd/amdgpu/soc15_common.h     WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \
_HWIP             124 drivers/gpu/drm/amd/amdgpu/soc15_common.h     (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
_HWIP             128 drivers/gpu/drm/amd/amdgpu/soc15_common.h     WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value)