_BASE_IDX 63 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ _BASE_IDX 75 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \ _BASE_IDX 85 drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ _BASE_IDX 63 drivers/gpu/drm/amd/amdgpu/soc15.h #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg _BASE_IDX 68 drivers/gpu/drm/amd/amdgpu/soc15.h { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } _BASE_IDX 28 drivers/gpu/drm/amd/amdgpu/soc15_common.h #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) _BASE_IDX 31 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \ _BASE_IDX 32 drivers/gpu/drm/amd/amdgpu/soc15_common.h (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ _BASE_IDX 36 drivers/gpu/drm/amd/amdgpu/soc15_common.h RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) _BASE_IDX 39 drivers/gpu/drm/amd/amdgpu/soc15_common.h RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset) _BASE_IDX 42 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) _BASE_IDX 45 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value) _BASE_IDX 48 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value) _BASE_IDX 53 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ _BASE_IDX 62 drivers/gpu/drm/amd/amdgpu/soc15_common.h tmp_ = RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \ _BASE_IDX 100 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t target_reg = adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg;\ _BASE_IDX 118 drivers/gpu/drm/amd/amdgpu/soc15_common.h uint32_t target_reg = adev->reg_offset[GC_HWIP][0][reg##_BASE_IDX] + reg;\ _BASE_IDX 123 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32_RLC((adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg), \ _BASE_IDX 124 drivers/gpu/drm/amd/amdgpu/soc15_common.h (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \ _BASE_IDX 128 drivers/gpu/drm/amd/amdgpu/soc15_common.h WREG32_RLC(((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset), value) _BASE_IDX 44 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_clk.c CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 63 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.c (MP1_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) _BASE_IDX 52 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 53 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c (CLK_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) _BASE_IDX 36 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.c (MP0_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name) _BASE_IDX 138 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 142 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 153 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 704 drivers/gpu/drm/amd/display/dc/dce120/dce120_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 37 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 41 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 46 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 170 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 174 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 179 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 190 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 201 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c .reg_name = MMHUB_BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 42 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 46 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 50 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 40 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 44 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 48 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 52 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 424 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 428 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 432 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 436 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 440 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 451 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 462 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ _BASE_IDX 38 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_vmid.h .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 287 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 291 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 295 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 299 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 303 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 314 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \ _BASE_IDX 325 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \ _BASE_IDX 160 drivers/gpu/drm/amd/display/dc/dm_services.h dm_write_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, value, __func__) _BASE_IDX 163 drivers/gpu/drm/amd/display/dc/dm_services.h dm_read_reg_func(ctx, reg + DCE_BASE.instance[0].segment[reg##_BASE_IDX] + inst_offset, __func__) _BASE_IDX 166 drivers/gpu/drm/amd/display/dc/dm_services.h generic_reg_update_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, \ _BASE_IDX 170 drivers/gpu/drm/amd/display/dc/dm_services.h generic_reg_set_ex(ctx, DCE_BASE.instance[0].segment[mm##reg_name##_BASE_IDX] + mm##reg_name + inst_offset, 0, \ _BASE_IDX 61 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name _BASE_IDX 64 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_factory_dce120.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 52 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name _BASE_IDX 55 drivers/gpu/drm/amd/display/dc/gpio/dce120/hw_translate_dce120.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 58 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name _BASE_IDX 61 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_factory_dcn10.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 52 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name _BASE_IDX 55 drivers/gpu/drm/amd/display/dc/gpio/dcn10/hw_translate_dcn10.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 61 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name _BASE_IDX 67 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_factory_dcn20.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 57 drivers/gpu/drm/amd/display/dc/gpio/dcn20/hw_translate_dcn20.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name _BASE_IDX 59 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name _BASE_IDX 65 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_factory_dcn21.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 57 drivers/gpu/drm/amd/display/dc/gpio/dcn21/hw_translate_dcn21.c BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name _BASE_IDX 84 drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 101 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 182 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 184 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ _BASE_IDX 180 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \