XFER              127 drivers/dma/dw/core.c 	channel_set_bit(dw, MASK.XFER, dwc->mask);
XFER              315 drivers/dma/dw/core.c 	status_xfer = dma_readl(dw, RAW.XFER);
XFER              319 drivers/dma/dw/core.c 		dma_writel(dw, CLEAR.XFER, dwc->mask);
XFER              479 drivers/dma/dw/core.c 	status_xfer = dma_readl(dw, RAW.XFER);
XFER              495 drivers/dma/dw/core.c 	channel_set_bit(dw, MASK.XFER, dw->all_chan_mask);
XFER              519 drivers/dma/dw/core.c 	channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
XFER              530 drivers/dma/dw/core.c 		channel_clear_bit(dw, MASK.XFER, (1 << 8) - 1);
XFER              961 drivers/dma/dw/core.c 	channel_clear_bit(dw, MASK.XFER, dw->all_chan_mask);
XFER             1038 drivers/dma/dw/core.c 	channel_clear_bit(dw, MASK.XFER, dwc->mask);
XFER             1190 drivers/dma/dw/core.c 	dma_writel(dw, CLEAR.XFER, dw->all_chan_mask);
XFER               56 drivers/dma/dw/regs.h 	DW_REG(XFER);
XFER               41 drivers/dma/idma64.c 	channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
XFER               71 drivers/dma/idma64.c 	channel_set_bit(idma64, MASK(XFER), idma64c->mask);
XFER              149 drivers/dma/idma64.c 			dma_writel(idma64, CLEAR(XFER), idma64c->mask);
XFER              176 drivers/dma/idma64.c 	status_xfer = dma_readl(idma64, RAW(XFER));
XFER              233 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	cp_wait(ctx, XFER, BUSY);
XFER             1344 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	cp_wait(ctx, XFER, BUSY);
XFER             3346 drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxnv50.c 	cp_wait(ctx, XFER, BUSY);