zpos              114 drivers/gpu/drm/arm/display/komeda/komeda_kms.c 	if (!last || (new->base.zpos > last->base.zpos)) {
zpos              121 drivers/gpu/drm/arm/display/komeda/komeda_kms.c 		if (new->base.zpos < node->base.zpos) {
zpos              124 drivers/gpu/drm/arm/display/komeda/komeda_kms.c 		} else if (node->base.zpos == new->base.zpos) {
zpos              132 drivers/gpu/drm/arm/display/komeda/komeda_kms.c 					 a->name, b->name, node->base.zpos);
zpos              187 drivers/gpu/drm/arm/display/komeda/komeda_kms.c 				 plane_st->zpos, plane_st->normalized_zpos);
zpos              150 drivers/gpu/drm/arm/display/komeda/komeda_plane.c 		state->base.zpos = kplane->layer->base.id;
zpos              573 drivers/gpu/drm/drm_atomic_uapi.c 		state->zpos = val;
zpos              636 drivers/gpu/drm/drm_atomic_uapi.c 		*val = state->zpos;
zpos              350 drivers/gpu/drm/drm_blend.c 				   unsigned int zpos,
zpos              359 drivers/gpu/drm/drm_blend.c 	drm_object_attach_property(&plane->base, prop, zpos);
zpos              364 drivers/gpu/drm/drm_blend.c 		plane->state->zpos = zpos;
zpos              365 drivers/gpu/drm/drm_blend.c 		plane->state->normalized_zpos = zpos;
zpos              389 drivers/gpu/drm/drm_blend.c 					     unsigned int zpos)
zpos              394 drivers/gpu/drm/drm_blend.c 					 "zpos", zpos, zpos);
zpos              398 drivers/gpu/drm/drm_blend.c 	drm_object_attach_property(&plane->base, prop, zpos);
zpos              403 drivers/gpu/drm/drm_blend.c 		plane->state->zpos = zpos;
zpos              404 drivers/gpu/drm/drm_blend.c 		plane->state->normalized_zpos = zpos;
zpos              416 drivers/gpu/drm/drm_blend.c 	if (sa->zpos != sb->zpos)
zpos              417 drivers/gpu/drm/drm_blend.c 		return sa->zpos - sb->zpos;
zpos              454 drivers/gpu/drm/drm_blend.c 				 plane_state->zpos);
zpos              504 drivers/gpu/drm/drm_blend.c 		if (old_plane_state->zpos != new_plane_state->zpos) {
zpos              628 drivers/gpu/drm/exynos/exynos5433_drm_decon.c 		ctx->configs[win].zpos = win - ctx->first_win;
zpos              628 drivers/gpu/drm/exynos/exynos7_drm_decon.c 		ctx->configs[i].zpos = i;
zpos              111 drivers/gpu/drm/exynos/exynos_drm_drv.h 	unsigned int zpos;
zpos             1068 drivers/gpu/drm/exynos/exynos_drm_fimd.c 		ctx->configs[i].zpos = i;
zpos              138 drivers/gpu/drm/exynos/exynos_drm_plane.c 		plane->state->zpos = exynos_plane->config->zpos;
zpos              286 drivers/gpu/drm/exynos/exynos_drm_plane.c 					      int zpos, bool immutable)
zpos              289 drivers/gpu/drm/exynos/exynos_drm_plane.c 		drm_plane_create_zpos_immutable_property(plane, zpos);
zpos              291 drivers/gpu/drm/exynos/exynos_drm_plane.c 		drm_plane_create_zpos_property(plane, zpos, 0, MAX_PLANE - 1);
zpos              320 drivers/gpu/drm/exynos/exynos_drm_plane.c 	exynos_plane_attach_zpos_property(&exynos_plane->base, config->zpos,
zpos              392 drivers/gpu/drm/exynos/exynos_drm_vidi.c 		plane_config.zpos = i;
zpos              124 drivers/gpu/drm/exynos/exynos_mixer.c 		.zpos = 0,
zpos              133 drivers/gpu/drm/exynos/exynos_mixer.c 		.zpos = 1,
zpos              142 drivers/gpu/drm/exynos/exynos_mixer.c 		.zpos = 2,
zpos              277 drivers/gpu/drm/imx/ipuv3-plane.c 	unsigned int zpos = (plane->type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
zpos              291 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_state->base.zpos = zpos;
zpos              292 drivers/gpu/drm/imx/ipuv3-plane.c 		ipu_state->base.normalized_zpos = zpos;
zpos              831 drivers/gpu/drm/imx/ipuv3-plane.c 	unsigned int zpos = (type == DRM_PLANE_TYPE_PRIMARY) ? 0 : 1;
zpos              863 drivers/gpu/drm/imx/ipuv3-plane.c 		drm_plane_create_zpos_property(&ipu_plane->base, zpos, 0, 1);
zpos              544 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 	unsigned int zpos;
zpos              609 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 	for (zpos = 0; zpos < mtk_crtc->layer_nr; zpos++) {
zpos              610 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		type = (zpos == 0) ? DRM_PLANE_TYPE_PRIMARY :
zpos              611 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 				(zpos == 1) ? DRM_PLANE_TYPE_CURSOR :
zpos              613 drivers/gpu/drm/mediatek/mtk_drm_crtc.c 		ret = mtk_plane_init(drm_dev, &mtk_crtc->planes[zpos],
zpos              575 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	return pa->state->zpos - pb->state->zpos;
zpos              101 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h 	uint8_t zpos;
zpos               90 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	INSTALL_RANGE_PROPERTY(zpos, ZPOS, 1, 255, 1);
zpos              118 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	SET_PROPERTY(zpos, ZPOS, uint8_t);
zpos              146 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	GET_PROPERTY(zpos, ZPOS, uint8_t);
zpos              169 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	drm_printf(p, "\tzpos=%u\n", pstate->zpos);
zpos              189 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 		mdp5_state->zpos = STAGE_BASE;
zpos              191 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 		mdp5_state->zpos = STAGE0 + drm_plane_index(plane);
zpos              575 drivers/gpu/drm/nouveau/dispnv50/wndw.c 	plane->state->zpos = nv50_wndw_zpos_default(plane);
zpos               25 drivers/gpu/drm/omapdrm/omap_crtc.c 	unsigned int zpos;
zpos              589 drivers/gpu/drm/omapdrm/omap_crtc.c 		omap_crtc_state->zpos = pri_state->zpos;
zpos              673 drivers/gpu/drm/omapdrm/omap_crtc.c 		plane_state->zpos = val;
zpos              691 drivers/gpu/drm/omapdrm/omap_crtc.c 		*val = omap_state->zpos;
zpos              726 drivers/gpu/drm/omapdrm/omap_crtc.c 	state->zpos = current_state->zpos;
zpos               93 drivers/gpu/drm/omapdrm/omap_plane.c 	plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY
zpos              190 drivers/gpu/drm/omapdrm/omap_plane.c 	plane->state->zpos = plane->type == DRM_PLANE_TYPE_PRIMARY
zpos              202 drivers/gpu/drm/omapdrm/omap_plane.c 		state->zpos = val;
zpos              217 drivers/gpu/drm/omapdrm/omap_plane.c 		*val = state->zpos;
zpos              694 drivers/gpu/drm/rcar-du/rcar_du_plane.c 	state->state.zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : 1;
zpos               70 drivers/gpu/drm/rcar-du/rcar_du_vsp.c 			.zpos = 0,
zpos              158 drivers/gpu/drm/rcar-du/rcar_du_vsp.c 		.zpos = state->state.zpos,
zpos              332 drivers/gpu/drm/rcar-du/rcar_du_vsp.c 	state->state.zpos = plane->type == DRM_PLANE_TYPE_PRIMARY ? 0 : 1;
zpos              118 drivers/gpu/drm/sti/sti_plane.c 	plane->state->zpos = sti_plane_get_default_zpos(plane->type);
zpos              124 drivers/gpu/drm/sti/sti_plane.c 	int zpos = sti_plane_get_default_zpos(type);
zpos              129 drivers/gpu/drm/sti/sti_plane.c 		drm_plane_create_zpos_property(drm_plane, zpos, 0, 6);
zpos              132 drivers/gpu/drm/sti/sti_plane.c 		drm_plane_create_zpos_immutable_property(drm_plane, zpos);
zpos               35 drivers/gpu/drm/sun4i/sun4i_layer.c 		plane->state->zpos = layer->id;
zpos               27 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 				  int overlay, bool enable, unsigned int zpos,
zpos               47 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	if (!enable || zpos != old_zpos) {
zpos               60 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
zpos               66 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
zpos               70 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
zpos               77 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 				       unsigned int zpos)
zpos              164 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		     SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
zpos              167 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 		     SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
zpos              279 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 	unsigned int zpos = plane->state->normalized_zpos;
zpos              290 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 				    layer->overlay, plane, zpos);
zpos              296 drivers/gpu/drm/sun4i/sun8i_ui_layer.c 			      true, zpos, old_zpos);
zpos               20 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 				  int overlay, bool enable, unsigned int zpos,
zpos               40 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	if (!enable || zpos != old_zpos) {
zpos               53 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos);
zpos               59 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos);
zpos               63 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 				   SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos),
zpos               70 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 				       unsigned int zpos)
zpos              204 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		     SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos),
zpos              207 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 		     SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos),
zpos              364 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 	unsigned int zpos = plane->state->normalized_zpos;
zpos              375 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 				    layer->overlay, plane, zpos);
zpos              381 drivers/gpu/drm/sun4i/sun8i_vi_layer.c 			      true, zpos, old_zpos);
zpos              302 drivers/gpu/drm/tegra/dc.c 	value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos);
zpos              712 drivers/gpu/drm/tegra/dc.c 	window.zpos = plane->state->normalized_zpos;
zpos              140 drivers/gpu/drm/tegra/dc.h 	unsigned int zpos;
zpos              413 drivers/gpu/drm/tegra/hub.c 	unsigned int zpos = plane->state->normalized_zpos;
zpos              446 drivers/gpu/drm/tegra/hub.c 	value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - zpos);
zpos               37 drivers/gpu/drm/tegra/plane.c 		plane->state->zpos = p->index;
zpos             1036 drivers/gpu/drm/vc4/vc4_plane.c 	plane->state->zpos = state->zpos;
zpos              363 drivers/media/platform/vsp1/vsp1_drm.c 	return vsp1->drm->inputs[rpf->entity.index].zpos;
zpos              838 drivers/media/platform/vsp1/vsp1_drm.c 		&cfg->mem[2], cfg->zpos);
zpos              857 drivers/media/platform/vsp1/vsp1_drm.c 	vsp1->drm->inputs[rpf_index].zpos = cfg->zpos;
zpos               63 drivers/media/platform/vsp1/vsp1_drm.h 		unsigned int zpos;
zpos               53 include/drm/drm_blend.h 				   unsigned int zpos,
zpos               56 include/drm/drm_blend.h 					     unsigned int zpos);
zpos              151 include/drm/drm_plane.h 	unsigned int zpos;
zpos               62 include/media/vsp1.h 	unsigned int zpos;