zplane 101 drivers/gpu/drm/zte/zx_plane.c static inline void zx_vl_set_update(struct zx_plane *zplane) zplane 103 drivers/gpu/drm/zte/zx_plane.c void __iomem *layer = zplane->layer; zplane 108 drivers/gpu/drm/zte/zx_plane.c static inline void zx_vl_rsz_set_update(struct zx_plane *zplane) zplane 110 drivers/gpu/drm/zte/zx_plane.c zx_writel(zplane->rsz + RSZ_VL_ENABLE_CFG, 1); zplane 147 drivers/gpu/drm/zte/zx_plane.c static void zx_vl_rsz_setup(struct zx_plane *zplane, uint32_t format, zplane 150 drivers/gpu/drm/zte/zx_plane.c void __iomem *rsz = zplane->rsz; zplane 178 drivers/gpu/drm/zte/zx_plane.c zx_vl_rsz_set_update(zplane); zplane 184 drivers/gpu/drm/zte/zx_plane.c struct zx_plane *zplane = to_zx_plane(plane); zplane 190 drivers/gpu/drm/zte/zx_plane.c void __iomem *layer = zplane->layer; zplane 191 drivers/gpu/drm/zte/zx_plane.c void __iomem *hbsc = zplane->hbsc; zplane 249 drivers/gpu/drm/zte/zx_plane.c zx_vl_rsz_setup(zplane, format, src_w, src_h, dst_w, dst_h); zplane 256 drivers/gpu/drm/zte/zx_plane.c zx_vl_set_update(zplane); zplane 262 drivers/gpu/drm/zte/zx_plane.c struct zx_plane *zplane = to_zx_plane(plane); zplane 263 drivers/gpu/drm/zte/zx_plane.c void __iomem *hbsc = zplane->hbsc; zplane 326 drivers/gpu/drm/zte/zx_plane.c static inline void zx_gl_set_update(struct zx_plane *zplane) zplane 328 drivers/gpu/drm/zte/zx_plane.c void __iomem *layer = zplane->layer; zplane 333 drivers/gpu/drm/zte/zx_plane.c static inline void zx_gl_rsz_set_update(struct zx_plane *zplane) zplane 335 drivers/gpu/drm/zte/zx_plane.c zx_writel(zplane->rsz + RSZ_ENABLE_CFG, 1); zplane 338 drivers/gpu/drm/zte/zx_plane.c static void zx_gl_rsz_setup(struct zx_plane *zplane, u32 src_w, u32 src_h, zplane 341 drivers/gpu/drm/zte/zx_plane.c void __iomem *rsz = zplane->rsz; zplane 346 drivers/gpu/drm/zte/zx_plane.c zx_gl_rsz_set_update(zplane); zplane 352 drivers/gpu/drm/zte/zx_plane.c struct zx_plane *zplane = to_zx_plane(plane); zplane 355 drivers/gpu/drm/zte/zx_plane.c void __iomem *layer = zplane->layer; zplane 356 drivers/gpu/drm/zte/zx_plane.c void __iomem *csc = zplane->csc; zplane 357 drivers/gpu/drm/zte/zx_plane.c void __iomem *hbsc = zplane->hbsc; zplane 425 drivers/gpu/drm/zte/zx_plane.c zx_gl_rsz_setup(zplane, src_w, src_h, dst_w, dst_h); zplane 432 drivers/gpu/drm/zte/zx_plane.c zx_gl_set_update(zplane); zplane 457 drivers/gpu/drm/zte/zx_plane.c struct zx_plane *zplane = to_zx_plane(plane); zplane 465 drivers/gpu/drm/zte/zx_plane.c zx_gl_rsz_set_update(zplane); zplane 466 drivers/gpu/drm/zte/zx_plane.c zx_gl_set_update(zplane); zplane 469 drivers/gpu/drm/zte/zx_plane.c zx_vl_rsz_set_update(zplane); zplane 470 drivers/gpu/drm/zte/zx_plane.c zx_vl_set_update(zplane); zplane 477 drivers/gpu/drm/zte/zx_plane.c static void zx_plane_hbsc_init(struct zx_plane *zplane) zplane 479 drivers/gpu/drm/zte/zx_plane.c void __iomem *hbsc = zplane->hbsc; zplane 495 drivers/gpu/drm/zte/zx_plane.c int zx_plane_init(struct drm_device *drm, struct zx_plane *zplane, zplane 499 drivers/gpu/drm/zte/zx_plane.c struct drm_plane *plane = &zplane->plane; zplane 500 drivers/gpu/drm/zte/zx_plane.c struct device *dev = zplane->dev; zplane 505 drivers/gpu/drm/zte/zx_plane.c zx_plane_hbsc_init(zplane); zplane 22 drivers/gpu/drm/zte/zx_plane.h int zx_plane_init(struct drm_device *drm, struct zx_plane *zplane, zplane 535 drivers/gpu/drm/zte/zx_vou.c struct zx_plane *zplane; zplane 546 drivers/gpu/drm/zte/zx_vou.c zplane = devm_kzalloc(dev, sizeof(*zplane), GFP_KERNEL); zplane 547 drivers/gpu/drm/zte/zx_vou.c if (!zplane) zplane 550 drivers/gpu/drm/zte/zx_vou.c zplane->dev = dev; zplane 553 drivers/gpu/drm/zte/zx_vou.c zplane->layer = vou->osd + MAIN_GL_OFFSET; zplane 554 drivers/gpu/drm/zte/zx_vou.c zplane->csc = vou->osd + MAIN_GL_CSC_OFFSET; zplane 555 drivers/gpu/drm/zte/zx_vou.c zplane->hbsc = vou->osd + MAIN_HBSC_OFFSET; zplane 556 drivers/gpu/drm/zte/zx_vou.c zplane->rsz = vou->otfppu + MAIN_RSZ_OFFSET; zplane 557 drivers/gpu/drm/zte/zx_vou.c zplane->bits = &zx_gl_bits[0]; zplane 564 drivers/gpu/drm/zte/zx_vou.c zplane->layer = vou->osd + AUX_GL_OFFSET; zplane 565 drivers/gpu/drm/zte/zx_vou.c zplane->csc = vou->osd + AUX_GL_CSC_OFFSET; zplane 566 drivers/gpu/drm/zte/zx_vou.c zplane->hbsc = vou->osd + AUX_HBSC_OFFSET; zplane 567 drivers/gpu/drm/zte/zx_vou.c zplane->rsz = vou->otfppu + AUX_RSZ_OFFSET; zplane 568 drivers/gpu/drm/zte/zx_vou.c zplane->bits = &zx_gl_bits[1]; zplane 584 drivers/gpu/drm/zte/zx_vou.c ret = zx_plane_init(drm, zplane, DRM_PLANE_TYPE_PRIMARY); zplane 590 drivers/gpu/drm/zte/zx_vou.c zcrtc->primary = &zplane->plane; zplane 613 drivers/gpu/drm/zte/zx_vou.c struct zx_plane *zplane = to_zx_plane(plane); zplane 614 drivers/gpu/drm/zte/zx_vou.c const struct vou_layer_bits *bits = zplane->bits; zplane 634 drivers/gpu/drm/zte/zx_vou.c struct zx_plane *zplane = to_zx_plane(plane); zplane 635 drivers/gpu/drm/zte/zx_vou.c const struct vou_layer_bits *bits = zplane->bits; zplane 643 drivers/gpu/drm/zte/zx_vou.c struct zx_plane *zplane; zplane 652 drivers/gpu/drm/zte/zx_vou.c zplane = devm_kzalloc(dev, sizeof(*zplane), GFP_KERNEL); zplane 653 drivers/gpu/drm/zte/zx_vou.c if (!zplane) { zplane 658 drivers/gpu/drm/zte/zx_vou.c zplane->layer = vou->osd + OSD_VL_OFFSET(i); zplane 659 drivers/gpu/drm/zte/zx_vou.c zplane->hbsc = vou->osd + HBSC_VL_OFFSET(i); zplane 660 drivers/gpu/drm/zte/zx_vou.c zplane->rsz = vou->otfppu + RSZ_VL_OFFSET(i); zplane 661 drivers/gpu/drm/zte/zx_vou.c zplane->bits = &zx_vl_bits[i]; zplane 663 drivers/gpu/drm/zte/zx_vou.c ret = zx_plane_init(drm, zplane, DRM_PLANE_TYPE_OVERLAY);