znum              985 arch/sparc/mm/srmmu.c 		int znum;
znum              987 arch/sparc/mm/srmmu.c 		for (znum = 0; znum < MAX_NR_ZONES; znum++)
znum              988 arch/sparc/mm/srmmu.c 			zones_size[znum] = zholes_size[znum] = 0;
znum             3157 drivers/dma/ppc4xx/adma.c 			int znum = 0;
znum             3163 drivers/dma/ppc4xx/adma.c 				znum++;
znum             3165 drivers/dma/ppc4xx/adma.c 				znum++;
znum             3169 drivers/dma/ppc4xx/adma.c 					index + znum);
znum             3486 drivers/dma/ppc4xx/adma.c 			int znum = 0;
znum             3493 drivers/dma/ppc4xx/adma.c 				znum++;
znum             3495 drivers/dma/ppc4xx/adma.c 				znum++;
znum             3497 drivers/dma/ppc4xx/adma.c 			iter = ppc440spe_get_group_entry(sw_desc, index + znum);
znum               36 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	const int znum =  zbc - 1;
znum               37 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	const u32 zoff = znum * 4;
znum               46 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	nvkm_mask(device, 0x418100 + ((znum / 4) * 4),
znum               47 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 			  0x0000007f << ((znum % 4) * 7),
znum               48 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 			  gr->zbc_color[zbc].format << ((znum % 4) * 7));
znum               55 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	const int znum =  zbc - 1;
znum               56 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	const u32 zoff = znum * 4;
znum               60 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 	nvkm_mask(device, 0x41814c + ((znum / 4) * 4),
znum               61 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 			  0x0000007f << ((znum % 4) * 7),
znum               62 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c 			  gr->zbc_depth[zbc].format << ((znum % 4) * 7));
znum               33 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	const int znum =  zbc - 1;
znum               34 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	const u32 zoff = znum * 4;
znum               38 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	nvkm_mask(device, 0x418198 + ((znum / 4) * 4),
znum               39 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 			  0x0000007f << ((znum % 4) * 7),
znum               40 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 			  gr->zbc_stencil[zbc].format << ((znum % 4) * 7));