zmode             138 drivers/gpu/drm/zte/zx_tvenc.c 		const struct zx_tvenc_mode *zmode = tvenc_modes[i];
zmode             140 drivers/gpu/drm/zte/zx_tvenc.c 		if (drm_mode_equal(mode, &zmode->mode))
zmode             141 drivers/gpu/drm/zte/zx_tvenc.c 			return zmode;
zmode             152 drivers/gpu/drm/zte/zx_tvenc.c 	const struct zx_tvenc_mode *zmode;
zmode             161 drivers/gpu/drm/zte/zx_tvenc.c 	zmode = zx_tvenc_find_zmode(mode);
zmode             162 drivers/gpu/drm/zte/zx_tvenc.c 	if (!zmode) {
zmode             167 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_VIDEO_INFO, zmode->video_info);
zmode             168 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_VIDEO_RES, zmode->video_res);
zmode             169 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_FIELD1_PARAM, zmode->field1_param);
zmode             170 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_FIELD2_PARAM, zmode->field2_param);
zmode             171 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_LINE_O_1, zmode->burst_line_odd1);
zmode             172 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_LINE_E_1, zmode->burst_line_even1);
zmode             173 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_LINE_O_2, zmode->burst_line_odd2);
zmode             174 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_LINE_E_2, zmode->burst_line_even2);
zmode             176 drivers/gpu/drm/zte/zx_tvenc.c 		  zmode->line_timing_param);
zmode             177 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_WEIGHT_VALUE, zmode->weight_value);
zmode             179 drivers/gpu/drm/zte/zx_tvenc.c 		  zmode->blank_black_level);
zmode             180 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_BURST_LEVEL, zmode->burst_level);
zmode             181 drivers/gpu/drm/zte/zx_tvenc.c 	zx_writel(tvenc->mmio + VENC_CONTROL_PARAM, zmode->control_param);
zmode             183 drivers/gpu/drm/zte/zx_tvenc.c 		  zmode->sub_carrier_phase1);
zmode             185 drivers/gpu/drm/zte/zx_tvenc.c 		  zmode->phase_line_incr_cvbs);
zmode             232 drivers/gpu/drm/zte/zx_tvenc.c 		const struct zx_tvenc_mode *zmode = tvenc_modes[i];
zmode             235 drivers/gpu/drm/zte/zx_tvenc.c 		mode = drm_mode_duplicate(connector->dev, &zmode->mode);
zmode             253 drivers/gpu/drm/zte/zx_tvenc.c 	const struct zx_tvenc_mode *zmode;
zmode             255 drivers/gpu/drm/zte/zx_tvenc.c 	zmode = zx_tvenc_find_zmode(mode);
zmode             256 drivers/gpu/drm/zte/zx_tvenc.c 	if (!zmode) {