zip 3731 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t zip:1; zip 3747 arch/mips/include/asm/octeon/cvmx-npei-defs.h uint64_t zip:1; zip 2239 arch/mips/include/asm/octeon/cvmx-npi-defs.h uint64_t zip:1; zip 2255 arch/mips/include/asm/octeon/cvmx-npi-defs.h uint64_t zip:1; zip 2308 arch/mips/include/asm/octeon/cvmx-npi-defs.h uint64_t zip:1; zip 2324 arch/mips/include/asm/octeon/cvmx-npi-defs.h uint64_t zip:1; zip 2379 arch/mips/include/asm/octeon/cvmx-npi-defs.h uint64_t zip:1; zip 2395 arch/mips/include/asm/octeon/cvmx-npi-defs.h uint64_t zip:1; zip 2446 arch/mips/include/asm/octeon/cvmx-npi-defs.h uint64_t zip:1; zip 2462 arch/mips/include/asm/octeon/cvmx-npi-defs.h uint64_t zip:1; zip 128 drivers/crypto/cavium/zip/zip_crypto.c struct zip_device *zip = NULL; zip 134 drivers/crypto/cavium/zip/zip_crypto.c zip = zip_get_device(zip_get_node_id()); zip 135 drivers/crypto/cavium/zip/zip_crypto.c if (!zip) zip 148 drivers/crypto/cavium/zip/zip_crypto.c ret = zip_deflate(zip_ops, zip_state, zip); zip 164 drivers/crypto/cavium/zip/zip_crypto.c struct zip_device *zip = NULL; zip 170 drivers/crypto/cavium/zip/zip_crypto.c zip = zip_get_device(zip_get_node_id()); zip 171 drivers/crypto/cavium/zip/zip_crypto.c if (!zip) zip 188 drivers/crypto/cavium/zip/zip_crypto.c ret = zip_inflate(zip_ops, zip_state, zip); zip 74 drivers/crypto/cavium/zip/zip_main.c struct zip_device *zip = NULL; zip 84 drivers/crypto/cavium/zip/zip_main.c zip = devm_kzalloc(&pdev->dev, sizeof(*zip), GFP_KERNEL); zip 86 drivers/crypto/cavium/zip/zip_main.c if (!zip) zip 89 drivers/crypto/cavium/zip/zip_main.c zip_dev[idx] = zip; zip 90 drivers/crypto/cavium/zip/zip_main.c zip->index = idx; zip 91 drivers/crypto/cavium/zip/zip_main.c return zip; zip 120 drivers/crypto/cavium/zip/zip_main.c static int zip_init_hw(struct zip_device *zip) zip 134 drivers/crypto/cavium/zip/zip_main.c cmd_ctl.u_reg64 = zip_reg_read(zip->reg_base + ZIP_CMD_CTL); zip 136 drivers/crypto/cavium/zip/zip_main.c zip_reg_write(cmd_ctl.u_reg64 & 0xFF, (zip->reg_base + ZIP_CMD_CTL)); zip 139 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_CMD_CTL)); zip 141 drivers/crypto/cavium/zip/zip_main.c constants.u_reg64 = zip_reg_read(zip->reg_base + ZIP_CONSTANTS); zip 142 drivers/crypto/cavium/zip/zip_main.c zip->depth = constants.s.depth; zip 143 drivers/crypto/cavium/zip/zip_main.c zip->onfsize = constants.s.onfsize; zip 144 drivers/crypto/cavium/zip/zip_main.c zip->ctxsize = constants.s.ctxsize; zip 147 drivers/crypto/cavium/zip/zip_main.c zip->depth, zip->onfsize, zip->ctxsize); zip 160 drivers/crypto/cavium/zip/zip_main.c (zip->reg_base + ZIP_QUEX_SBUF_CTL(q))); zip 163 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_QUEX_SBUF_CTL(q))); zip 167 drivers/crypto/cavium/zip/zip_main.c memset(&zip->iq[q], 0x0, sizeof(struct zip_iq)); zip 169 drivers/crypto/cavium/zip/zip_main.c spin_lock_init(&zip->iq[q].lock); zip 171 drivers/crypto/cavium/zip/zip_main.c if (zip_cmd_qbuf_alloc(zip, q)) { zip 174 drivers/crypto/cavium/zip/zip_main.c zip_cmd_qbuf_free(zip, q); zip 180 drivers/crypto/cavium/zip/zip_main.c zip->iq[q].sw_tail = zip->iq[q].sw_head; zip 181 drivers/crypto/cavium/zip/zip_main.c zip->iq[q].hw_tail = zip->iq[q].sw_head; zip 185 drivers/crypto/cavium/zip/zip_main.c que_sbuf_addr.s.ptr = (__pa(zip->iq[q].sw_head) >> zip 192 drivers/crypto/cavium/zip/zip_main.c (zip->reg_base + ZIP_QUEX_SBUF_ADDR(q))); zip 195 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_QUEX_SBUF_ADDR(q))); zip 198 drivers/crypto/cavium/zip/zip_main.c zip->iq[q].sw_head, zip->iq[q].sw_tail, zip 199 drivers/crypto/cavium/zip/zip_main.c zip->iq[q].hw_tail); zip 212 drivers/crypto/cavium/zip/zip_main.c zip_reg_write(que_ena.u_reg64, (zip->reg_base + ZIP_QUE_ENA)); zip 215 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_QUE_ENA)); zip 222 drivers/crypto/cavium/zip/zip_main.c (zip->reg_base + ZIP_QUEX_MAP(q))); zip 225 drivers/crypto/cavium/zip/zip_main.c zip_reg_read(zip->reg_base + ZIP_QUEX_MAP(q))); zip 231 drivers/crypto/cavium/zip/zip_main.c zip_reg_write(que_pri.u_reg64, (zip->reg_base + ZIP_QUE_PRI)); zip 233 drivers/crypto/cavium/zip/zip_main.c zip_msg("QUE_PRI %016llx", zip_reg_read(zip->reg_base + ZIP_QUE_PRI)); zip 241 drivers/crypto/cavium/zip/zip_main.c struct zip_device *zip = NULL; zip 244 drivers/crypto/cavium/zip/zip_main.c zip = zip_alloc_device(pdev); zip 245 drivers/crypto/cavium/zip/zip_main.c if (!zip) zip 248 drivers/crypto/cavium/zip/zip_main.c dev_info(dev, "Found ZIP device %d %x:%x on Node %d\n", zip->index, zip 251 drivers/crypto/cavium/zip/zip_main.c pci_set_drvdata(pdev, zip); zip 252 drivers/crypto/cavium/zip/zip_main.c zip->pdev = pdev; zip 279 drivers/crypto/cavium/zip/zip_main.c zip->reg_base = pci_ioremap_bar(pdev, PCI_CFG_ZIP_PF_BAR0); zip 280 drivers/crypto/cavium/zip/zip_main.c if (!zip->reg_base) { zip 287 drivers/crypto/cavium/zip/zip_main.c err = zip_init_hw(zip); zip 294 drivers/crypto/cavium/zip/zip_main.c if (zip->reg_base) zip 295 drivers/crypto/cavium/zip/zip_main.c iounmap(zip->reg_base); zip 305 drivers/crypto/cavium/zip/zip_main.c zip_dev[zip->index] = NULL; zip 306 drivers/crypto/cavium/zip/zip_main.c devm_kfree(dev, zip); zip 313 drivers/crypto/cavium/zip/zip_main.c struct zip_device *zip = pci_get_drvdata(pdev); zip 317 drivers/crypto/cavium/zip/zip_main.c if (!zip) zip 320 drivers/crypto/cavium/zip/zip_main.c if (zip->reg_base) { zip 323 drivers/crypto/cavium/zip/zip_main.c zip_reg_write(cmd_ctl.u_reg64, (zip->reg_base + ZIP_CMD_CTL)); zip 324 drivers/crypto/cavium/zip/zip_main.c iounmap(zip->reg_base); zip 335 drivers/crypto/cavium/zip/zip_main.c zip_cmd_qbuf_free(zip, q); zip 339 drivers/crypto/cavium/zip/zip_main.c zip_dev[zip->index] = NULL; zip 470 drivers/crypto/cavium/zip/zip_main.c struct zip_device *zip; zip 477 drivers/crypto/cavium/zip/zip_main.c zip = zip_dev[index]; zip 478 drivers/crypto/cavium/zip/zip_main.c st = &zip->stats; zip 482 drivers/crypto/cavium/zip/zip_main.c val = zip_reg_read((zip->reg_base + zip 57 drivers/crypto/cavium/zip/zip_mem.c int zip_cmd_qbuf_alloc(struct zip_device *zip, int q) zip 59 drivers/crypto/cavium/zip/zip_mem.c zip->iq[q].sw_head = (u64 *)__get_free_pages((GFP_KERNEL | GFP_DMA), zip 62 drivers/crypto/cavium/zip/zip_mem.c if (!zip->iq[q].sw_head) zip 65 drivers/crypto/cavium/zip/zip_mem.c memset(zip->iq[q].sw_head, 0, ZIP_CMD_QBUF_SIZE); zip 67 drivers/crypto/cavium/zip/zip_mem.c zip_dbg("cmd_qbuf_alloc[%d] Success : %p\n", q, zip->iq[q].sw_head); zip 76 drivers/crypto/cavium/zip/zip_mem.c void zip_cmd_qbuf_free(struct zip_device *zip, int q) zip 78 drivers/crypto/cavium/zip/zip_mem.c zip_dbg("Freeing cmd_qbuf 0x%lx\n", zip->iq[q].sw_tail); zip 80 drivers/crypto/cavium/zip/zip_mem.c free_pages((u64)zip->iq[q].sw_tail, get_order(ZIP_CMD_QBUF_SIZE)); zip 54 drivers/crypto/cavium/zip/zip_mem.h void zip_cmd_qbuf_free(struct zip_device *zip, int q); zip 62 drivers/crypto/cavium/zip/zip_mem.h int zip_cmd_qbuf_alloc(struct zip_device *zip, int q); zip 93 drivers/crypto/hisilicon/zip/zip_main.c struct hisi_zip *zip = NULL; zip 101 drivers/crypto/hisilicon/zip/zip_main.c zip = hisi_zip; zip 106 drivers/crypto/hisilicon/zip/zip_main.c return zip; zip 112 drivers/crypto/hisilicon/zip/zip_main.c struct hisi_zip *zip = NULL; zip 116 drivers/crypto/hisilicon/zip/zip_main.c zip = find_zip_device_numa(node); zip 118 drivers/crypto/hisilicon/zip/zip_main.c zip = list_first_entry(&hisi_zip_list, struct hisi_zip, list); zip 122 drivers/crypto/hisilicon/zip/zip_main.c return zip; zip 1028 drivers/staging/octeon/octeon-stubs.h uint64_t zip:1; zip 1063 drivers/staging/octeon/octeon-stubs.h uint64_t zip:1; zip 1098 drivers/staging/octeon/octeon-stubs.h uint64_t zip:1; zip 1129 drivers/staging/octeon/octeon-stubs.h uint64_t zip:1;