zcrtc             218 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(crtc);
zcrtc             220 drivers/gpu/drm/zte/zx_vou.c 	return zcrtc->vou;
zcrtc             226 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(crtc);
zcrtc             227 drivers/gpu/drm/zte/zx_vou.c 	struct zx_vou_hw *vou = zcrtc->vou;
zcrtc             234 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(crtc);
zcrtc             235 drivers/gpu/drm/zte/zx_vou.c 	struct zx_vou_hw *vou = zcrtc->vou;
zcrtc             237 drivers/gpu/drm/zte/zx_vou.c 	void __iomem *dither = zcrtc->dither;
zcrtc             238 drivers/gpu/drm/zte/zx_vou.c 	void __iomem *csc = zcrtc->chncsc;
zcrtc             239 drivers/gpu/drm/zte/zx_vou.c 	bool is_main = zcrtc->chn_type == VOU_CHN_MAIN;
zcrtc             263 drivers/gpu/drm/zte/zx_vou.c 		       zcrtc->chn_type << id);
zcrtc             292 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(crtc);
zcrtc             293 drivers/gpu/drm/zte/zx_vou.c 	struct zx_vou_hw *vou = zcrtc->vou;
zcrtc             294 drivers/gpu/drm/zte/zx_vou.c 	const struct zx_crtc_bits *bits = zcrtc->bits;
zcrtc             347 drivers/gpu/drm/zte/zx_vou.c static inline void vou_chn_set_update(struct zx_crtc *zcrtc)
zcrtc             349 drivers/gpu/drm/zte/zx_vou.c 	zx_writel(zcrtc->chnreg + CHN_UPDATE, 1);
zcrtc             357 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(crtc);
zcrtc             358 drivers/gpu/drm/zte/zx_vou.c 	struct zx_vou_hw *vou = zcrtc->vou;
zcrtc             359 drivers/gpu/drm/zte/zx_vou.c 	const struct zx_crtc_regs *regs = zcrtc->regs;
zcrtc             360 drivers/gpu/drm/zte/zx_vou.c 	const struct zx_crtc_bits *bits = zcrtc->bits;
zcrtc             429 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_W_MASK,
zcrtc             431 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL1, CHN_SCREEN_H_MASK,
zcrtc             435 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_INTERLACE_BUF_CTRL, CHN_INTERLACE_EN,
zcrtc             439 drivers/gpu/drm/zte/zx_vou.c 	vou_chn_set_update(zcrtc);
zcrtc             442 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, CHN_ENABLE);
zcrtc             446 drivers/gpu/drm/zte/zx_vou.c 	ret = clk_set_rate(zcrtc->pixclk, mode->clock * 1000);
zcrtc             452 drivers/gpu/drm/zte/zx_vou.c 	ret = clk_prepare_enable(zcrtc->pixclk);
zcrtc             460 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(crtc);
zcrtc             461 drivers/gpu/drm/zte/zx_vou.c 	const struct zx_crtc_bits *bits = zcrtc->bits;
zcrtc             462 drivers/gpu/drm/zte/zx_vou.c 	struct zx_vou_hw *vou = zcrtc->vou;
zcrtc             464 drivers/gpu/drm/zte/zx_vou.c 	clk_disable_unprepare(zcrtc->pixclk);
zcrtc             469 drivers/gpu/drm/zte/zx_vou.c 	zx_writel_mask(zcrtc->chnreg + CHN_CTRL0, CHN_ENABLE, 0);
zcrtc             501 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(crtc);
zcrtc             503 drivers/gpu/drm/zte/zx_vou.c 	u32 int_frame_mask = zcrtc->bits->int_frame_mask;
zcrtc             513 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(crtc);
zcrtc             517 drivers/gpu/drm/zte/zx_vou.c 		       zcrtc->bits->int_frame_mask, 0);
zcrtc             536 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc;
zcrtc             539 drivers/gpu/drm/zte/zx_vou.c 	zcrtc = devm_kzalloc(dev, sizeof(*zcrtc), GFP_KERNEL);
zcrtc             540 drivers/gpu/drm/zte/zx_vou.c 	if (!zcrtc)
zcrtc             543 drivers/gpu/drm/zte/zx_vou.c 	zcrtc->vou = vou;
zcrtc             544 drivers/gpu/drm/zte/zx_vou.c 	zcrtc->chn_type = chn_type;
zcrtc             558 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->chnreg = vou->osd + OSD_MAIN_CHN;
zcrtc             559 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->chncsc = vou->osd + MAIN_CHN_CSC_OFFSET;
zcrtc             560 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->dither = vou->osd + MAIN_DITHER_OFFSET;
zcrtc             561 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->regs = &main_crtc_regs;
zcrtc             562 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->bits = &main_crtc_bits;
zcrtc             569 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->chnreg = vou->osd + OSD_AUX_CHN;
zcrtc             570 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->chncsc = vou->osd + AUX_CHN_CSC_OFFSET;
zcrtc             571 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->dither = vou->osd + AUX_DITHER_OFFSET;
zcrtc             572 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->regs = &aux_crtc_regs;
zcrtc             573 drivers/gpu/drm/zte/zx_vou.c 		zcrtc->bits = &aux_crtc_bits;
zcrtc             576 drivers/gpu/drm/zte/zx_vou.c 	zcrtc->pixclk = devm_clk_get(dev, (chn_type == VOU_CHN_MAIN) ?
zcrtc             578 drivers/gpu/drm/zte/zx_vou.c 	if (IS_ERR(zcrtc->pixclk)) {
zcrtc             579 drivers/gpu/drm/zte/zx_vou.c 		ret = PTR_ERR(zcrtc->pixclk);
zcrtc             590 drivers/gpu/drm/zte/zx_vou.c 	zcrtc->primary = &zplane->plane;
zcrtc             592 drivers/gpu/drm/zte/zx_vou.c 	ret = drm_crtc_init_with_planes(drm, &zcrtc->crtc, zcrtc->primary, NULL,
zcrtc             599 drivers/gpu/drm/zte/zx_vou.c 	drm_crtc_helper_add(&zcrtc->crtc, &zx_crtc_helper_funcs);
zcrtc             602 drivers/gpu/drm/zte/zx_vou.c 		vou->main_crtc = zcrtc;
zcrtc             604 drivers/gpu/drm/zte/zx_vou.c 		vou->aux_crtc = zcrtc;
zcrtc             611 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(plane->state->crtc);
zcrtc             612 drivers/gpu/drm/zte/zx_vou.c 	struct zx_vou_hw *vou = zcrtc->vou;
zcrtc             616 drivers/gpu/drm/zte/zx_vou.c 	if (zcrtc->chn_type == VOU_CHN_MAIN) {
zcrtc             632 drivers/gpu/drm/zte/zx_vou.c 	struct zx_crtc *zcrtc = to_zx_crtc(old_state->crtc);
zcrtc             633 drivers/gpu/drm/zte/zx_vou.c 	struct zx_vou_hw *vou = zcrtc->vou;
zcrtc             671 drivers/gpu/drm/zte/zx_vou.c static inline void zx_osd_int_update(struct zx_crtc *zcrtc)
zcrtc             673 drivers/gpu/drm/zte/zx_vou.c 	struct drm_crtc *crtc = &zcrtc->crtc;
zcrtc             676 drivers/gpu/drm/zte/zx_vou.c 	vou_chn_set_update(zcrtc);