zbc_stencil        24 drivers/gpu/drm/nouveau/include/nvkm/subdev/ltc.h 	u32 zbc_stencil[NVKM_LTC_MAX_ZBC_CNT];
zbc_stencil       112 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h 	struct gf100_gr_zbc_stencil zbc_stencil[NVKM_LTC_MAX_ZBC_CNT];
zbc_stencil        36 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	if (gr->zbc_stencil[zbc].format)
zbc_stencil        37 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 		nvkm_wr32(device, 0x41815c + zoff, gr->zbc_stencil[zbc].ds);
zbc_stencil        40 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 			  gr->zbc_stencil[zbc].format << ((znum % 4) * 7));
zbc_stencil        51 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 		if (gr->zbc_stencil[i].format) {
zbc_stencil        52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 			if (gr->zbc_stencil[i].format != format)
zbc_stencil        54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 			if (gr->zbc_stencil[i].ds != ds)
zbc_stencil        56 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 			if (gr->zbc_stencil[i].l2 != l2) {
zbc_stencil        69 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	gr->zbc_stencil[zbc].format = format;
zbc_stencil        70 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	gr->zbc_stencil[zbc].ds = ds;
zbc_stencil        71 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c 	gr->zbc_stencil[zbc].l2 = l2;
zbc_stencil        61 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c 	ltc->zbc_stencil[index] = stencil;
zbc_stencil       104 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c 			ltc->func->zbc_clear_stencil(ltc, i, ltc->zbc_stencil[i]);