zbc 49 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) zbc 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_color[zbc].format) { zbc 53 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405804, gr->zbc_color[zbc].ds[0]); zbc 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405808, gr->zbc_color[zbc].ds[1]); zbc 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x40580c, gr->zbc_color[zbc].ds[2]); zbc 56 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405810, gr->zbc_color[zbc].ds[3]); zbc 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405814, gr->zbc_color[zbc].format); zbc 59 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405820, zbc); zbc 68 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c int zbc = -ENOSPC, i; zbc 84 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c zbc = (zbc < 0) ? i : zbc; zbc 88 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (zbc < 0) zbc 89 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return zbc; zbc 91 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c memcpy(gr->zbc_color[zbc].ds, ds, sizeof(gr->zbc_color[zbc].ds)); zbc 92 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c memcpy(gr->zbc_color[zbc].l2, l2, sizeof(gr->zbc_color[zbc].l2)); zbc 93 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_color[zbc].format = format; zbc 94 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_ltc_zbc_color_get(ltc, zbc, l2); zbc 95 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_color(gr, zbc); zbc 96 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return zbc; zbc 100 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gf100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) zbc 103 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->zbc_depth[zbc].format) zbc 104 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405818, gr->zbc_depth[zbc].ds); zbc 105 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x40581c, gr->zbc_depth[zbc].format); zbc 106 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_wr32(device, 0x405820, zbc); zbc 115 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c int zbc = -ENOSPC, i; zbc 129 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c zbc = (zbc < 0) ? i : zbc; zbc 133 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (zbc < 0) zbc 134 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return zbc; zbc 136 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_depth[zbc].format = format; zbc 137 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_depth[zbc].ds = ds; zbc 138 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->zbc_depth[zbc].l2 = l2; zbc 139 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c nvkm_ltc_zbc_depth_get(ltc, zbc, l2); zbc 140 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_depth(gr, zbc); zbc 141 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c return zbc; zbc 967 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->zbc->stencil_get) { zbc 968 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->stencil_get(gr, 1, 0x00, 0x00); s++; zbc 969 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->stencil_get(gr, 1, 0x01, 0x01); s++; zbc 970 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->stencil_get(gr, 1, 0xff, 0xff); s++; zbc 975 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_color(gr, index); zbc 977 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_depth(gr, index); zbc 979 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c if (gr->func->zbc->clear_stencil) { zbc 981 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c gr->func->zbc->clear_stencil(gr, index); zbc 2472 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c .zbc = &gf100_gr_zbc, zbc 152 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h void (*clear_color)(struct gf100_gr *, int zbc); zbc 153 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h void (*clear_depth)(struct gf100_gr *, int zbc); zbc 156 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h void (*clear_stencil)(struct gf100_gr *, int zbc); zbc 202 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h const struct gf100_gr_func_zbc *zbc; zbc 137 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c .zbc = &gf100_gr_zbc, zbc 135 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c .zbc = &gf100_gr_zbc, zbc 109 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c .zbc = &gf100_gr_zbc, zbc 174 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c .zbc = &gf100_gr_zbc, zbc 200 drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c .zbc = &gf100_gr_zbc, zbc 482 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c .zbc = &gf100_gr_zbc, zbc 378 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c .zbc = &gf100_gr_zbc, zbc 129 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c .zbc = &gf100_gr_zbc, zbc 187 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c .zbc = &gf100_gr_zbc, zbc 296 drivers/gpu/drm/nouveau/nvkm/engine/gr/gk20a.c .zbc = &gf100_gr_zbc, zbc 422 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c .zbc = &gf100_gr_zbc, zbc 190 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c .zbc = &gf100_gr_zbc, zbc 78 drivers/gpu/drm/nouveau/nvkm/engine/gr/gm20b.c .zbc = &gf100_gr_zbc, zbc 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gp100_gr_zbc_clear_color(struct gf100_gr *gr, int zbc) zbc 36 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c const int znum = zbc - 1; zbc 39 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c if (gr->zbc_color[zbc].format) { zbc 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x418010 + zoff, gr->zbc_color[zbc].ds[0]); zbc 41 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x41804c + zoff, gr->zbc_color[zbc].ds[1]); zbc 42 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x418088 + zoff, gr->zbc_color[zbc].ds[2]); zbc 43 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x4180c4 + zoff, gr->zbc_color[zbc].ds[3]); zbc 48 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gr->zbc_color[zbc].format << ((znum % 4) * 7)); zbc 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gp100_gr_zbc_clear_depth(struct gf100_gr *gr, int zbc) zbc 55 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c const int znum = zbc - 1; zbc 58 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c if (gr->zbc_depth[zbc].format) zbc 59 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c nvkm_wr32(device, 0x418110 + zoff, gr->zbc_depth[zbc].ds); zbc 62 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c gr->zbc_depth[zbc].format << ((znum % 4) * 7)); zbc 128 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c .zbc = &gp100_gr_zbc, zbc 30 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gp102_gr_zbc_clear_stencil(struct gf100_gr *gr, int zbc) zbc 33 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c const int znum = zbc - 1; zbc 36 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c if (gr->zbc_stencil[zbc].format) zbc 37 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c nvkm_wr32(device, 0x41815c + zoff, gr->zbc_stencil[zbc].ds); zbc 40 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->zbc_stencil[zbc].format << ((znum % 4) * 7)); zbc 48 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c int zbc = -ENOSPC, i; zbc 62 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c zbc = (zbc < 0) ? i : zbc; zbc 66 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c if (zbc < 0) zbc 67 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c return zbc; zbc 69 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->zbc_stencil[zbc].format = format; zbc 70 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->zbc_stencil[zbc].ds = ds; zbc 71 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->zbc_stencil[zbc].l2 = l2; zbc 72 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c nvkm_ltc_zbc_stencil_get(ltc, zbc, l2); zbc 73 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c gr->func->zbc->clear_stencil(gr, zbc); zbc 74 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c return zbc; zbc 124 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c .zbc = &gp102_gr_zbc, zbc 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp104.c .zbc = &gp102_gr_zbc, zbc 54 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c .zbc = &gp102_gr_zbc, zbc 52 drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c .zbc = &gp102_gr_zbc, zbc 113 drivers/gpu/drm/nouveau/nvkm/engine/gr/gv100.c .zbc = &gp102_gr_zbc, zbc 139 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.c ltc->zbc_max = min(func->zbc, NVKM_LTC_MAX_ZBC_CNT) - 1; zbc 244 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.c .zbc = 16, zbc 45 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.c .zbc = 16, zbc 140 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.c .zbc = 16, zbc 52 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.c .zbc = 16, zbc 64 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.c .zbc = 16, zbc 39 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.c .zbc = 16, zbc 19 drivers/gpu/drm/nouveau/nvkm/subdev/ltc/priv.h int zbc;