WB_EC_CONFIG       74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1,
WB_EC_CONFIG       98 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c 	REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0,
WB_EC_CONFIG       55 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	SRI(WB_EC_CONFIG, CNV, inst),\
WB_EC_CONFIG      218 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h 	uint32_t WB_EC_CONFIG;
WB_EC_CONFIG       59 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SRI2(WB_EC_CONFIG, CNV, inst),\
WB_EC_CONFIG      107 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\
WB_EC_CONFIG      108 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\
WB_EC_CONFIG      109 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\
WB_EC_CONFIG      110 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WB_TEST_CLK_SEL, mask_sh),\
WB_EC_CONFIG      111 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\
WB_EC_CONFIG      112 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WB_LB_SD_DIS, mask_sh),\
WB_EC_CONFIG      113 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\
WB_EC_CONFIG      114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_MODE_SEL, mask_sh),\
WB_EC_CONFIG      115 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_DIS, mask_sh),\
WB_EC_CONFIG      116 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_FORCE, mask_sh),\
WB_EC_CONFIG      117 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WBSCL_LB_MEM_PWR_STATE, mask_sh),\
WB_EC_CONFIG      118 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WB_RAM_PW_SAVE_MODE, mask_sh),\
WB_EC_CONFIG      119 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WB_EC_CONFIG, WBSCL_LUT_MEM_PWR_STATE, mask_sh),\
WB_EC_CONFIG      359 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	uint32_t WB_EC_CONFIG;