WBSCL_TAP_CONTROL   72 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SRI2(WBSCL_TAP_CONTROL, WBSCL, inst),\
WBSCL_TAP_CONTROL  171 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, mask_sh),\
WBSCL_TAP_CONTROL  172 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, mask_sh),\
WBSCL_TAP_CONTROL  173 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, mask_sh),\
WBSCL_TAP_CONTROL  174 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, mask_sh),\
WBSCL_TAP_CONTROL  378 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	uint32_t WBSCL_TAP_CONTROL;
WBSCL_TAP_CONTROL  756 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_Y_RGB, h_taps_luma - 1);
WBSCL_TAP_CONTROL  757 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_H_NUM_OF_TAPS_CBCR, h_taps_chroma - 1);
WBSCL_TAP_CONTROL  836 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_Y_RGB, v_taps_luma - 1);
WBSCL_TAP_CONTROL  837 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 	REG_UPDATE(WBSCL_TAP_CONTROL, WBSCL_V_NUM_OF_TAPS_CBCR, v_taps_chroma - 1);