WBSCL_ROUND_OFFSET 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, 0x40); WBSCL_ROUND_OFFSET 266 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c REG_UPDATE(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, 0x200); WBSCL_ROUND_OFFSET 80 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SRI2(WBSCL_ROUND_OFFSET, WBSCL, inst),\ WBSCL_ROUND_OFFSET 187 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_Y_RGB, mask_sh),\ WBSCL_ROUND_OFFSET 188 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_ROUND_OFFSET, WBSCL_ROUND_OFFSET_CBCR, mask_sh),\ WBSCL_ROUND_OFFSET 386 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_ROUND_OFFSET;