WBSCL_COEF_RAM_TAP_DATA   70 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SRI2(WBSCL_COEF_RAM_TAP_DATA, WBSCL, inst),\
WBSCL_COEF_RAM_TAP_DATA  165 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF, mask_sh),\
WBSCL_COEF_RAM_TAP_DATA  166 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_EVEN_TAP_COEF_EN, mask_sh),\
WBSCL_COEF_RAM_TAP_DATA  167 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF, mask_sh),\
WBSCL_COEF_RAM_TAP_DATA  168 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_TAP_DATA, WBSCL_COEF_RAM_ODD_TAP_COEF_EN, mask_sh),\
WBSCL_COEF_RAM_TAP_DATA  376 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	uint32_t WBSCL_COEF_RAM_TAP_DATA;
WBSCL_COEF_RAM_TAP_DATA  706 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 			REG_SET_4(WBSCL_COEF_RAM_TAP_DATA, 0,