WBSCL_COEF_RAM_SELECT   69 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SRI2(WBSCL_COEF_RAM_SELECT, WBSCL, inst),\
WBSCL_COEF_RAM_SELECT  162 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_TAP_PAIR_IDX, mask_sh),\
WBSCL_COEF_RAM_SELECT  163 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_PHASE, mask_sh),\
WBSCL_COEF_RAM_SELECT  164 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_SELECT, WBSCL_COEF_RAM_FILTER_TYPE, mask_sh),\
WBSCL_COEF_RAM_SELECT  375 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	uint32_t WBSCL_COEF_RAM_SELECT;
WBSCL_COEF_RAM_SELECT  701 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb_scl.c 			REG_SET_3(WBSCL_COEF_RAM_SELECT, 0,