WBSCL_COEF_RAM_CONFLICT_STATUS   82 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SRI2(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL, inst),\
WBSCL_COEF_RAM_CONFLICT_STATUS  194 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_FLAG, mask_sh),\
WBSCL_COEF_RAM_CONFLICT_STATUS  195 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_ACK, mask_sh),\
WBSCL_COEF_RAM_CONFLICT_STATUS  196 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_MASK, mask_sh),\
WBSCL_COEF_RAM_CONFLICT_STATUS  197 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_STATUS, mask_sh),\
WBSCL_COEF_RAM_CONFLICT_STATUS  198 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(WBSCL_COEF_RAM_CONFLICT_STATUS, WBSCL_HOST_CONFLICT_INT_TYPE, mask_sh),\
WBSCL_COEF_RAM_CONFLICT_STATUS  388 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	uint32_t WBSCL_COEF_RAM_CONFLICT_STATUS;