WBSCL_CLAMP_CBCR 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c REG_UPDATE(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, 0x3fe); WBSCL_CLAMP_CBCR 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c REG_UPDATE(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, 0x1); WBSCL_CLAMP_CBCR 90 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SRI2(WBSCL_CLAMP_CBCR, WBSCL, inst),\ WBSCL_CLAMP_CBCR 212 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_UPPER_CBCR, mask_sh),\ WBSCL_CLAMP_CBCR 213 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h SF(WBSCL_CLAMP_CBCR, WBSCL_CLAMP_LOWER_CBCR, mask_sh),\ WBSCL_CLAMP_CBCR 396 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h uint32_t WBSCL_CLAMP_CBCR;