WBIF0_SMU_WM_CONTROL 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\ WBIF0_SMU_WM_CONTROL 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, mask_sh),\ WBIF0_SMU_WM_CONTROL 276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, mask_sh),\ WBIF0_SMU_WM_CONTROL 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_mmhubbub.h SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, mask_sh)