xin_id 182 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c .xin_id = _xinid, \ xin_id 447 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h u32 xin_id; xin_id 28 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h u32 xin_id; xin_id 56 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 xin_id, u32 value) xin_id 67 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c if (!vbif || xin_id >= MAX_XIN_COUNT || xin_id >= 16) xin_id 72 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c if (xin_id >= 8) { xin_id 73 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c xin_id -= 8; xin_id 78 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c bit_off = (xin_id & 0x7) * 4; xin_id 86 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 xin_id, bool rd, u32 limit) xin_id 98 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off += (xin_id / 4) * 4; xin_id 99 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c bit_off = (xin_id % 4) * 8; xin_id 107 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 xin_id, bool rd) xin_id 120 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_off += (xin_id / 4) * 4; xin_id 121 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c bit_off = (xin_id % 4) * 8; xin_id 129 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 xin_id, bool enable) xin_id 137 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= BIT(xin_id); xin_id 139 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val &= ~BIT(xin_id); xin_id 145 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 xin_id) xin_id 152 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c return (reg_val & BIT(xin_id)) ? true : false; xin_id 156 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c u32 xin_id, u32 level, u32 remap_level) xin_id 166 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_high = ((xin_id & 0x8) >> 3) * 4 + (level * 8); xin_id 167 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_shift = (xin_id & 0x7) * 4; xin_id 184 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c static void dpu_hw_set_write_gather_en(struct dpu_hw_vbif *vbif, u32 xin_id) xin_id 189 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c if (!vbif || xin_id >= MAX_XIN_COUNT) xin_id 195 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.c reg_val |= BIT(xin_id); xin_id 27 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h u32 xin_id, bool rd, u32 limit); xin_id 37 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h u32 xin_id, bool rd); xin_id 46 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h u32 xin_id, bool enable); xin_id 55 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h u32 xin_id); xin_id 65 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h u32 xin_id, u32 level, u32 remap_level); xin_id 74 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h u32 xin_id, u32 value); xin_id 93 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_vbif.h void (*set_write_gather_en)(struct dpu_hw_vbif *vbif, u32 xin_id); xin_id 377 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c ot_params.xin_id = pdpu->pipe_hw->cap->xin_id; xin_id 403 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c qos_params.xin_id = pdpu->pipe_hw->cap->xin_id; xin_id 410 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c qos_params.xin_id, qos_params.is_rt, xin_id 1367 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c (u32 *) &cfg->xin_id); xin_id 75 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(u32 pnum, u32 xin_id, u32 rd_lim, u32 vbif_idx), xin_id 76 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_ARGS(pnum, xin_id, rd_lim, vbif_idx), xin_id 79 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field(u32, xin_id) xin_id 85 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __entry->xin_id = xin_id; xin_id 90 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __entry->pnum, __entry->xin_id, __entry->rd_lim, xin_id 857 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_PROTO(enum dpu_vbif index, u32 xin_id), xin_id 858 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_ARGS(index, xin_id), xin_id 861 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __field( u32, xin_id ) xin_id 865 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h __entry->xin_id = xin_id; xin_id 867 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h TP_printk("index:%d xin_id:%u", __entry->index, __entry->xin_id) xin_id 20 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c static int _dpu_vbif_wait_for_xin_halt(struct dpu_hw_vbif *vbif, u32 xin_id) xin_id 33 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c status = vbif->ops.get_halt_ctrl(vbif, xin_id); xin_id 37 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c status = vbif->ops.get_halt_ctrl(vbif, xin_id); xin_id 46 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c vbif->idx - VBIF_0, xin_id); xin_id 50 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c vbif->idx - VBIF_0, xin_id); xin_id 91 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c vbif->idx - VBIF_0, params->xin_id, xin_id 130 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c params->xin_id, params->rd); xin_id 137 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c vbif->idx - VBIF_0, params->xin_id, ot_lim); xin_id 182 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c vbif->ops.set_write_gather_en(vbif, params->xin_id); xin_id 189 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c trace_dpu_perf_set_ot(params->num, params->xin_id, ot_lim, xin_id 194 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c vbif->ops.set_limit_conf(vbif, params->xin_id, params->rd, ot_lim); xin_id 196 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c vbif->ops.set_halt_ctrl(vbif, params->xin_id, true); xin_id 198 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c ret = _dpu_vbif_wait_for_xin_halt(vbif, params->xin_id); xin_id 200 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c trace_dpu_vbif_wait_xin_halt_fail(vbif->idx, params->xin_id); xin_id 202 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c vbif->ops.set_halt_ctrl(vbif, params->xin_id, false); xin_id 253 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c params->vbif_idx, params->xin_id, i, xin_id 255 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c vbif->ops.set_qos_remap(vbif, params->xin_id, i, xin_id 11 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h u32 xin_id; xin_id 23 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h u32 xin_id; xin_id 39 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.h u32 xin_id;