xfeatures_mask 63 arch/x86/include/asm/fpu/api.h extern int cpu_has_xfeatures(u64 xfeatures_mask, const char **feature_name); xfeatures_mask 95 arch/x86/include/asm/fpu/internal.h xsave->header.xcomp_bv = XCOMP_BV_COMPACTED_FORMAT | xfeatures_mask; xfeatures_mask 44 arch/x86/include/asm/fpu/xstate.h extern u64 xfeatures_mask; xfeatures_mask 257 arch/x86/kernel/fpu/signal.c u64 init_bv = xfeatures_mask & ~XFEATURE_MASK_FPSSE; xfeatures_mask 261 arch/x86/kernel/fpu/signal.c u64 init_bv = xfeatures_mask & ~xbv; xfeatures_mask 361 arch/x86/kernel/fpu/signal.c u64 init_bv = xfeatures_mask & ~xfeatures; xfeatures_mask 392 arch/x86/kernel/fpu/signal.c u64 init_bv = xfeatures_mask & ~XFEATURE_MASK_FPSSE; xfeatures_mask 468 arch/x86/kernel/fpu/signal.c fx_sw_reserved.xfeatures = xfeatures_mask; xfeatures_mask 59 arch/x86/kernel/fpu/xstate.c u64 xfeatures_mask __read_mostly; xfeatures_mask 63 arch/x86/kernel/fpu/xstate.c static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; xfeatures_mask 79 arch/x86/kernel/fpu/xstate.c u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask; xfeatures_mask 161 arch/x86/kernel/fpu/xstate.c if ((xfeatures & xfeatures_mask) == xfeatures_mask) xfeatures_mask 188 arch/x86/kernel/fpu/xstate.c xfeatures = (xfeatures_mask & ~xfeatures) >> 2; xfeatures_mask 216 arch/x86/kernel/fpu/xstate.c if (!boot_cpu_has(X86_FEATURE_XSAVE) || !xfeatures_mask) xfeatures_mask 223 arch/x86/kernel/fpu/xstate.c WARN_ONCE((xfeatures_mask & XFEATURE_MASK_SUPERVISOR), xfeatures_mask 226 arch/x86/kernel/fpu/xstate.c xfeatures_mask &= ~XFEATURE_MASK_SUPERVISOR; xfeatures_mask 229 arch/x86/kernel/fpu/xstate.c xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); xfeatures_mask 239 arch/x86/kernel/fpu/xstate.c return !!(xfeatures_mask & (1UL << xfeature)); xfeatures_mask 345 arch/x86/kernel/fpu/xstate.c unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8]; xfeatures_mask 418 arch/x86/kernel/fpu/xstate.c init_fpstate.xsave.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask; xfeatures_mask 478 arch/x86/kernel/fpu/xstate.c if (hdr->xfeatures & (~xfeatures_mask | XFEATURE_MASK_SUPERVISOR)) xfeatures_mask 703 arch/x86/kernel/fpu/xstate.c xfeatures_mask = 0; xfeatures_mask 739 arch/x86/kernel/fpu/xstate.c xfeatures_mask = eax + ((u64)edx << 32); xfeatures_mask 741 arch/x86/kernel/fpu/xstate.c if ((xfeatures_mask & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) { xfeatures_mask 747 arch/x86/kernel/fpu/xstate.c pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask); xfeatures_mask 756 arch/x86/kernel/fpu/xstate.c xfeatures_mask &= ~BIT(i); xfeatures_mask 759 arch/x86/kernel/fpu/xstate.c xfeatures_mask &= fpu__get_supported_xfeatures_mask(); xfeatures_mask 771 arch/x86/kernel/fpu/xstate.c update_regset_xstate_info(fpu_user_xstate_size, xfeatures_mask & ~XFEATURE_MASK_SUPERVISOR); xfeatures_mask 779 arch/x86/kernel/fpu/xstate.c xfeatures_mask, xfeatures_mask 798 arch/x86/kernel/fpu/xstate.c xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); xfeatures_mask 846 arch/x86/kernel/fpu/xstate.c WARN_ONCE(!(xfeatures_mask & BIT_ULL(xfeature_nr)),