VddcOffset        102 drivers/gpu/drm/amd/powerplay/inc/smu71_discrete.h     uint16_t    VddcOffset;
VddcOffset         97 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h 	uint16_t    VddcOffset;
VddcOffset         95 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h 	uint16_t    VddcOffset;
VddcOffset        124 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h 	uint16_t    VddcOffset;
VddcOffset        129 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h 	uint16_t    VddcOffset;
VddcOffset        160 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     uint16_t    VddcOffset;
VddcOffset        966 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			state->VddcOffset = 0;
VddcOffset        969 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 			state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
VddcOffset        984 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
VddcOffset        808 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
VddcOffset        817 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
VddcOffset        735 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			state->VddcOffset = 0;
VddcOffset        738 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 			state->VddcOffset = (uint16_t)(hwmgr->dyn_state.vddc_dependency_on_sclk->entries[0].v - ulv_voltage);
VddcOffset        753 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
VddcOffset        744 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
VddcOffset        755 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
VddcOffset        488 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
VddcOffset        496 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
VddcOffset        548 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	state->VddcOffset = (uint16_t) table_info->us_ulv_voltage_offset;
VddcOffset        556 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 	CONVERT_FROM_HOST_TO_SMC_US(state->VddcOffset);
VddcOffset       3138 drivers/gpu/drm/radeon/ci_dpm.c 			state->VddcOffset = 0;
VddcOffset       3140 drivers/gpu/drm/radeon/ci_dpm.c 			state->VddcOffset =
VddcOffset       3154 drivers/gpu/drm/radeon/ci_dpm.c 	state->VddcOffset = cpu_to_be16(state->VddcOffset);
VddcOffset        160 drivers/gpu/drm/radeon/smu7_discrete.h     uint16_t    VddcOffset;