xfc_dst_y_delta_drq_limit  896 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	double xfc_dst_y_delta_drq_limit;
xfc_dst_y_delta_drq_limit 1358 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
xfc_dst_y_delta_drq_limit 1522 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
xfc_dst_y_delta_drq_limit  896 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	double xfc_dst_y_delta_drq_limit;
xfc_dst_y_delta_drq_limit 1358 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
xfc_dst_y_delta_drq_limit 1522 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);
xfc_dst_y_delta_drq_limit  943 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	double xfc_dst_y_delta_drq_limit;
xfc_dst_y_delta_drq_limit 1428 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	xfc_dst_y_delta_drq_limit = xfc_remote_surface_flip_latency;
xfc_dst_y_delta_drq_limit 1622 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		disp_dlg_regs->dst_y_delta_drq_limit = dml_ceil(xfc_dst_y_delta_drq_limit, 1);