CNV_SOURCE_SIZE    78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.c 	REG_UPDATE_2(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, params->cnv_params.src_width,
CNV_SOURCE_SIZE    64 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SRI2(CNV_SOURCE_SIZE, CNV, inst),\
CNV_SOURCE_SIZE   139 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(CNV_SOURCE_SIZE, CNV_SOURCE_WIDTH, mask_sh),\
CNV_SOURCE_SIZE   140 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	SF(CNV_SOURCE_SIZE, CNV_SOURCE_HEIGHT, mask_sh),\
CNV_SOURCE_SIZE   364 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dwb.h 	uint32_t CNV_SOURCE_SIZE;