VceLevel         1027 drivers/gpu/drm/amd/amdgpu/kv_dpm.c 				   offsetof(SMU7_Fusion_DpmTable, VceLevel),
VceLevel          271 drivers/gpu/drm/amd/powerplay/inc/smu72_discrete.h 	SMU72_Discrete_ExtClkLevel          VceLevel[SMU72_MAX_LEVELS_VCE];
VceLevel          255 drivers/gpu/drm/amd/powerplay/inc/smu73_discrete.h     SMU73_Discrete_ExtClkLevel          VceLevel                [SMU73_MAX_LEVELS_VCE];
VceLevel          287 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h 	SMU74_Discrete_ExtClkLevel          VceLevel[SMU74_MAX_LEVELS_VCE];
VceLevel          293 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h 	SMU75_Discrete_ExtClkLevel          VceLevel                [SMU75_MAX_LEVELS_VCE];
VceLevel          329 drivers/gpu/drm/amd/powerplay/inc/smu7_discrete.h     SMU7_Discrete_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
VceLevel          236 drivers/gpu/drm/amd/powerplay/inc/smu7_fusion.h     SMU7_Fusion_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
VceLevel         1570 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->VceLevel[count].Frequency = vce_table->entries[count].evclk;
VceLevel         1571 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->VceLevel[count].MinVoltage =
VceLevel         1573 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->VceLevel[count].MinPhases = 1;
VceLevel         1576 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 				table->VceLevel[count].Frequency, &dividers);
VceLevel         1581 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
VceLevel         1583 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
VceLevel         1584 drivers/gpu/drm/amd/powerplay/smumgr/ci_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_US(table->VceLevel[count].MinVoltage);
VceLevel         1437 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
VceLevel         1438 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->VceLevel[count].MinVoltage = 0;
VceLevel         1439 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->VceLevel[count].MinVoltage |=
VceLevel         1441 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->VceLevel[count].MinVoltage |=
VceLevel         1444 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
VceLevel         1448 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 				table->VceLevel[count].Frequency, &dividers);
VceLevel         1453 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
VceLevel         1455 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
VceLevel         1456 drivers/gpu/drm/amd/powerplay/smumgr/fiji_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
VceLevel         1303 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
VceLevel         1304 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->VceLevel[count].MinVoltage = 0;
VceLevel         1305 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->VceLevel[count].MinVoltage |=
VceLevel         1317 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->VceLevel[count].MinVoltage |=
VceLevel         1319 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
VceLevel         1323 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 				table->VceLevel[count].Frequency, &dividers);
VceLevel         1328 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
VceLevel         1330 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
VceLevel         1331 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
VceLevel         1384 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->VceLevel[count].Frequency =
VceLevel         1386 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->VceLevel[count].MinVoltage.Vddc =
VceLevel         1389 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->VceLevel[count].MinVoltage.VddGfx =
VceLevel         1393 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->VceLevel[count].MinVoltage.Vddci =
VceLevel         1396 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->VceLevel[count].MinVoltage.Phases = 1;
VceLevel         1400 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 					table->VceLevel[count].Frequency, &dividers);
VceLevel         1405 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
VceLevel         1407 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
VceLevel         1220 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->VceLevel[count].Frequency = mm_table->entries[count].eclk;
VceLevel         1221 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->VceLevel[count].MinVoltage = 0;
VceLevel         1222 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->VceLevel[count].MinVoltage |=
VceLevel         1234 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->VceLevel[count].MinVoltage |=
VceLevel         1236 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->VceLevel[count].MinVoltage |= 1 << PHASES_SHIFT;
VceLevel         1240 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 				table->VceLevel[count].Frequency, &dividers);
VceLevel         1245 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
VceLevel         1247 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
VceLevel         1248 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c 		CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].MinVoltage);
VceLevel         2702 drivers/gpu/drm/radeon/ci_dpm.c 		table->VceLevel[count].Frequency =
VceLevel         2704 drivers/gpu/drm/radeon/ci_dpm.c 		table->VceLevel[count].MinVoltage =
VceLevel         2706 drivers/gpu/drm/radeon/ci_dpm.c 		table->VceLevel[count].MinPhases = 1;
VceLevel         2710 drivers/gpu/drm/radeon/ci_dpm.c 						     table->VceLevel[count].Frequency, false, &dividers);
VceLevel         2714 drivers/gpu/drm/radeon/ci_dpm.c 		table->VceLevel[count].Divider = (u8)dividers.post_divider;
VceLevel         2716 drivers/gpu/drm/radeon/ci_dpm.c 		table->VceLevel[count].Frequency = cpu_to_be32(table->VceLevel[count].Frequency);
VceLevel         2717 drivers/gpu/drm/radeon/ci_dpm.c 		table->VceLevel[count].MinVoltage = cpu_to_be16(table->VceLevel[count].MinVoltage);
VceLevel          945 drivers/gpu/drm/radeon/kv_dpm.c 				   offsetof(SMU7_Fusion_DpmTable, VceLevel),
VceLevel          328 drivers/gpu/drm/radeon/smu7_discrete.h     SMU7_Discrete_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];
VceLevel          236 drivers/gpu/drm/radeon/smu7_fusion.h     SMU7_Fusion_ExtClkLevel           VceLevel                [SMU7_MAX_LEVELS_VCE];