xc 35 arch/mips/math-emu/dp_2008class.c switch(xc) { xc 49 arch/mips/math-emu/dp_2008class.c pr_err("Unknown class: %d\n", xc); xc 27 arch/mips/math-emu/dp_add.c switch (CLPAIR(xc, yc)) { xc 26 arch/mips/math-emu/dp_cmp.c if (ieee754_class_nan(xc) || ieee754_class_nan(yc)) { xc 28 arch/mips/math-emu/dp_cmp.c xc == IEEE754_CLASS_SNAN || yc == IEEE754_CLASS_SNAN) xc 29 arch/mips/math-emu/dp_div.c switch (CLPAIR(xc, yc)) { xc 31 arch/mips/math-emu/dp_fmax.c switch (CLPAIR(xc, yc)) { xc 158 arch/mips/math-emu/dp_fmax.c switch (CLPAIR(xc, yc)) { xc 31 arch/mips/math-emu/dp_fmin.c switch (CLPAIR(xc, yc)) { xc 158 arch/mips/math-emu/dp_fmin.c switch (CLPAIR(xc, yc)) { xc 29 arch/mips/math-emu/dp_fsp.c switch (xc) { xc 77 arch/mips/math-emu/dp_maddf.c if (xc == IEEE754_CLASS_SNAN) xc 83 arch/mips/math-emu/dp_maddf.c if (xc == IEEE754_CLASS_QNAN) xc 92 arch/mips/math-emu/dp_maddf.c switch (CLPAIR(xc, yc)) { xc 37 arch/mips/math-emu/dp_mul.c switch (CLPAIR(xc, yc)) { xc 29 arch/mips/math-emu/dp_rint.c if (xc == IEEE754_CLASS_SNAN) xc 32 arch/mips/math-emu/dp_rint.c if ((xc == IEEE754_CLASS_QNAN) || xc 33 arch/mips/math-emu/dp_rint.c (xc == IEEE754_CLASS_INF) || xc 34 arch/mips/math-emu/dp_rint.c (xc == IEEE754_CLASS_ZERO)) xc 32 arch/mips/math-emu/dp_sqrt.c switch (xc) { xc 27 arch/mips/math-emu/dp_sub.c switch (CLPAIR(xc, yc)) { xc 26 arch/mips/math-emu/dp_tint.c switch (xc) { xc 26 arch/mips/math-emu/dp_tlong.c switch (xc) { xc 18 arch/mips/math-emu/ieee754dp.c return xc; xc 39 arch/mips/math-emu/ieee754int.h static inline int ieee754_class_nan(int xc) xc 41 arch/mips/math-emu/ieee754int.h return xc >= IEEE754_CLASS_SNAN; xc 45 arch/mips/math-emu/ieee754int.h unsigned int xm; int xe; int xs __maybe_unused; int xc xc 77 arch/mips/math-emu/ieee754int.h #define EXPLODEXSP EXPLODESP(x, xc, xs, xe, xm) xc 83 arch/mips/math-emu/ieee754int.h u64 xm; int xe; int xs __maybe_unused; int xc xc 115 arch/mips/math-emu/ieee754int.h #define EXPLODEXDP EXPLODEDP(x, xc, xs, xe, xm) xc 141 arch/mips/math-emu/ieee754int.h #define FLUSHXDP FLUSHDP(x, xc, xs, xe, xm) xc 144 arch/mips/math-emu/ieee754int.h #define FLUSHXSP FLUSHSP(x, xc, xs, xe, xm) xc 18 arch/mips/math-emu/ieee754sp.c return xc; xc 35 arch/mips/math-emu/sp_2008class.c switch(xc) { xc 49 arch/mips/math-emu/sp_2008class.c pr_err("Unknown class: %d\n", xc); xc 27 arch/mips/math-emu/sp_add.c switch (CLPAIR(xc, yc)) { xc 26 arch/mips/math-emu/sp_cmp.c if (ieee754_class_nan(xc) || ieee754_class_nan(yc)) { xc 28 arch/mips/math-emu/sp_cmp.c xc == IEEE754_CLASS_SNAN || yc == IEEE754_CLASS_SNAN) xc 29 arch/mips/math-emu/sp_div.c switch (CLPAIR(xc, yc)) { xc 33 arch/mips/math-emu/sp_fdp.c switch (xc) { xc 31 arch/mips/math-emu/sp_fmax.c switch (CLPAIR(xc, yc)) { xc 158 arch/mips/math-emu/sp_fmax.c switch (CLPAIR(xc, yc)) { xc 31 arch/mips/math-emu/sp_fmin.c switch (CLPAIR(xc, yc)) { xc 158 arch/mips/math-emu/sp_fmin.c switch (CLPAIR(xc, yc)) { xc 45 arch/mips/math-emu/sp_maddf.c if (xc == IEEE754_CLASS_SNAN) xc 51 arch/mips/math-emu/sp_maddf.c if (xc == IEEE754_CLASS_QNAN) xc 60 arch/mips/math-emu/sp_maddf.c switch (CLPAIR(xc, yc)) { xc 37 arch/mips/math-emu/sp_mul.c switch (CLPAIR(xc, yc)) { xc 29 arch/mips/math-emu/sp_rint.c if (xc == IEEE754_CLASS_SNAN) xc 32 arch/mips/math-emu/sp_rint.c if ((xc == IEEE754_CLASS_QNAN) || xc 33 arch/mips/math-emu/sp_rint.c (xc == IEEE754_CLASS_INF) || xc 34 arch/mips/math-emu/sp_rint.c (xc == IEEE754_CLASS_ZERO)) xc 25 arch/mips/math-emu/sp_sqrt.c switch (xc) { xc 27 arch/mips/math-emu/sp_sub.c switch (CLPAIR(xc, yc)) { xc 26 arch/mips/math-emu/sp_tint.c switch (xc) { xc 26 arch/mips/math-emu/sp_tlong.c switch (xc) { xc 178 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 179 arch/powerpc/kvm/book3s_xive.c struct xive_q *q = &xc->queues[prio]; xc 184 arch/powerpc/kvm/book3s_xive.c if (xc->esc_virq[prio]) xc 188 arch/powerpc/kvm/book3s_xive.c xc->esc_virq[prio] = irq_create_mapping(NULL, q->esc_irq); xc 189 arch/powerpc/kvm/book3s_xive.c if (!xc->esc_virq[prio]) { xc 191 arch/powerpc/kvm/book3s_xive.c prio, xc->server_num); xc 197 arch/powerpc/kvm/book3s_xive.c vcpu->kvm->arch.lpid, xc->server_num); xc 200 arch/powerpc/kvm/book3s_xive.c vcpu->kvm->arch.lpid, xc->server_num, prio); xc 203 arch/powerpc/kvm/book3s_xive.c prio, xc->server_num); xc 208 arch/powerpc/kvm/book3s_xive.c pr_devel("Escalation %s irq %d (prio %d)\n", name, xc->esc_virq[prio], prio); xc 210 arch/powerpc/kvm/book3s_xive.c rc = request_irq(xc->esc_virq[prio], xive_esc_irq, xc 214 arch/powerpc/kvm/book3s_xive.c prio, xc->server_num); xc 217 arch/powerpc/kvm/book3s_xive.c xc->esc_virq_names[prio] = name; xc 228 arch/powerpc/kvm/book3s_xive.c struct irq_data *d = irq_get_irq_data(xc->esc_virq[prio]); xc 239 arch/powerpc/kvm/book3s_xive.c irq_dispose_mapping(xc->esc_virq[prio]); xc 240 arch/powerpc/kvm/book3s_xive.c xc->esc_virq[prio] = 0; xc 247 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 248 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive *xive = xc->xive; xc 249 arch/powerpc/kvm/book3s_xive.c struct xive_q *q = &xc->queues[prio]; xc 260 arch/powerpc/kvm/book3s_xive.c prio, xc->server_num); xc 272 arch/powerpc/kvm/book3s_xive.c rc = xive_native_configure_queue(xc->vp_id, q, prio, qpage, xc 276 arch/powerpc/kvm/book3s_xive.c prio, xc->server_num); xc 316 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc; xc 325 arch/powerpc/kvm/book3s_xive.c xc = vcpu->arch.xive_vcpu; xc 326 arch/powerpc/kvm/book3s_xive.c if (WARN_ON(!xc)) xc 329 arch/powerpc/kvm/book3s_xive.c q = &xc->queues[prio]; xc 335 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 339 arch/powerpc/kvm/book3s_xive.c if (WARN_ON(!xc)) xc 341 arch/powerpc/kvm/book3s_xive.c if (!xc->valid) xc 344 arch/powerpc/kvm/book3s_xive.c q = &xc->queues[prio]; xc 826 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 828 arch/powerpc/kvm/book3s_xive.c if (!xc) xc 832 arch/powerpc/kvm/book3s_xive.c return (u64)xc->cppr << KVM_REG_PPC_ICP_CPPR_SHIFT | xc 833 arch/powerpc/kvm/book3s_xive.c (u64)xc->mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT | xc 839 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 844 arch/powerpc/kvm/book3s_xive.c if (!xc || !xive) xc 854 arch/powerpc/kvm/book3s_xive.c xc->server_num, cppr, mfrr, xisr); xc 866 arch/powerpc/kvm/book3s_xive.c xc->hw_cppr = xc->cppr = cppr; xc 874 arch/powerpc/kvm/book3s_xive.c xc->mfrr = mfrr; xc 876 arch/powerpc/kvm/book3s_xive.c xive_irq_trigger(&xc->vp_ipi_data); xc 888 arch/powerpc/kvm/book3s_xive.c xc->delayed_irq = xisr; xc 1076 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 1093 arch/powerpc/kvm/book3s_xive.c if (state->act_server != xc->server_num) xc 1134 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc, int irq) xc 1152 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 1159 arch/powerpc/kvm/book3s_xive.c if (!xc) xc 1162 arch/powerpc/kvm/book3s_xive.c pr_devel("cleanup_vcpu(cpu=%d)\n", xc->server_num); xc 1165 arch/powerpc/kvm/book3s_xive.c xc->valid = false; xc 1169 arch/powerpc/kvm/book3s_xive.c xive_vm_esb_load(&xc->vp_ipi_data, XIVE_ESB_SET_PQ_01); xc 1173 arch/powerpc/kvm/book3s_xive.c if (xc->esc_virq[i]) { xc 1174 arch/powerpc/kvm/book3s_xive.c if (xc->xive->single_escalation) xc 1175 arch/powerpc/kvm/book3s_xive.c xive_cleanup_single_escalation(vcpu, xc, xc 1176 arch/powerpc/kvm/book3s_xive.c xc->esc_virq[i]); xc 1177 arch/powerpc/kvm/book3s_xive.c free_irq(xc->esc_virq[i], vcpu); xc 1178 arch/powerpc/kvm/book3s_xive.c irq_dispose_mapping(xc->esc_virq[i]); xc 1179 arch/powerpc/kvm/book3s_xive.c kfree(xc->esc_virq_names[i]); xc 1184 arch/powerpc/kvm/book3s_xive.c xive_native_disable_vp(xc->vp_id); xc 1191 arch/powerpc/kvm/book3s_xive.c struct xive_q *q = &xc->queues[i]; xc 1193 arch/powerpc/kvm/book3s_xive.c xive_native_disable_queue(xc->vp_id, q, i); xc 1202 arch/powerpc/kvm/book3s_xive.c if (xc->vp_ipi) { xc 1203 arch/powerpc/kvm/book3s_xive.c xive_cleanup_irq_data(&xc->vp_ipi_data); xc 1204 arch/powerpc/kvm/book3s_xive.c xive_native_free_irq(xc->vp_ipi); xc 1207 arch/powerpc/kvm/book3s_xive.c kfree(xc); xc 1218 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc; xc 1247 arch/powerpc/kvm/book3s_xive.c xc = kzalloc(sizeof(*xc), GFP_KERNEL); xc 1248 arch/powerpc/kvm/book3s_xive.c if (!xc) { xc 1253 arch/powerpc/kvm/book3s_xive.c vcpu->arch.xive_vcpu = xc; xc 1254 arch/powerpc/kvm/book3s_xive.c xc->xive = xive; xc 1255 arch/powerpc/kvm/book3s_xive.c xc->vcpu = vcpu; xc 1256 arch/powerpc/kvm/book3s_xive.c xc->server_num = cpu; xc 1257 arch/powerpc/kvm/book3s_xive.c xc->vp_id = vp_id; xc 1258 arch/powerpc/kvm/book3s_xive.c xc->mfrr = 0xff; xc 1259 arch/powerpc/kvm/book3s_xive.c xc->valid = true; xc 1261 arch/powerpc/kvm/book3s_xive.c r = xive_native_get_vp_info(xc->vp_id, &xc->vp_cam, &xc->vp_chip_id); xc 1267 arch/powerpc/kvm/book3s_xive.c vcpu->arch.xive_cam_word = cpu_to_be32(xc->vp_cam | TM_QW1W2_VO); xc 1270 arch/powerpc/kvm/book3s_xive.c xc->vp_ipi = xive_native_alloc_irq(); xc 1271 arch/powerpc/kvm/book3s_xive.c if (!xc->vp_ipi) { xc 1276 arch/powerpc/kvm/book3s_xive.c pr_devel(" IPI=0x%x\n", xc->vp_ipi); xc 1278 arch/powerpc/kvm/book3s_xive.c r = xive_native_populate_irq_data(xc->vp_ipi, &xc->vp_ipi_data); xc 1286 arch/powerpc/kvm/book3s_xive.c r = xive_native_enable_vp(xc->vp_id, xive->single_escalation); xc 1300 arch/powerpc/kvm/book3s_xive.c struct xive_q *q = &xc->queues[i]; xc 1315 arch/powerpc/kvm/book3s_xive.c r = xive_native_configure_queue(xc->vp_id, xc 1331 arch/powerpc/kvm/book3s_xive.c r = xive_native_configure_irq(xc->vp_ipi, xc->vp_id, 0, XICS_IPI); xc 1333 arch/powerpc/kvm/book3s_xive.c xive_vm_esb_load(&xc->vp_ipi_data, XIVE_ESB_SET_PQ_00); xc 1455 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 1456 arch/powerpc/kvm/book3s_xive.c if (!xc) xc 1459 arch/powerpc/kvm/book3s_xive.c if (xc->queues[j].qpage) xc 1460 arch/powerpc/kvm/book3s_xive.c xive_pre_save_queue(xive, &xc->queues[j]); xc 1623 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 1625 arch/powerpc/kvm/book3s_xive.c if (!xc) xc 1628 arch/powerpc/kvm/book3s_xive.c if (xc->delayed_irq == irq) { xc 1629 arch/powerpc/kvm/book3s_xive.c xc->delayed_irq = 0; xc 2046 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 2050 arch/powerpc/kvm/book3s_xive.c struct xive_q *q = &xc->queues[i]; xc 2053 arch/powerpc/kvm/book3s_xive.c if (!q->qpage && !xc->esc_virq[i]) xc 2066 arch/powerpc/kvm/book3s_xive.c if (xc->esc_virq[i]) { xc 2067 arch/powerpc/kvm/book3s_xive.c struct irq_data *d = irq_get_irq_data(xc->esc_virq[i]); xc 2075 arch/powerpc/kvm/book3s_xive.c xc->esc_virq[i], pq, xd->eoi_page); xc 2105 arch/powerpc/kvm/book3s_xive.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 2107 arch/powerpc/kvm/book3s_xive.c if (!xc) xc 2112 arch/powerpc/kvm/book3s_xive.c xc->server_num, xc->cppr, xc->hw_cppr, xc 2113 arch/powerpc/kvm/book3s_xive.c xc->mfrr, xc->pending, xc 2114 arch/powerpc/kvm/book3s_xive.c xc->stat_rm_h_xirr, xc->stat_vm_h_xirr); xc 2118 arch/powerpc/kvm/book3s_xive.c t_rm_h_xirr += xc->stat_rm_h_xirr; xc 2119 arch/powerpc/kvm/book3s_xive.c t_rm_h_ipoll += xc->stat_rm_h_ipoll; xc 2120 arch/powerpc/kvm/book3s_xive.c t_rm_h_cppr += xc->stat_rm_h_cppr; xc 2121 arch/powerpc/kvm/book3s_xive.c t_rm_h_eoi += xc->stat_rm_h_eoi; xc 2122 arch/powerpc/kvm/book3s_xive.c t_rm_h_ipi += xc->stat_rm_h_ipi; xc 2123 arch/powerpc/kvm/book3s_xive.c t_vm_h_xirr += xc->stat_vm_h_xirr; xc 2124 arch/powerpc/kvm/book3s_xive.c t_vm_h_ipoll += xc->stat_vm_h_ipoll; xc 2125 arch/powerpc/kvm/book3s_xive.c t_vm_h_cppr += xc->stat_vm_h_cppr; xc 2126 arch/powerpc/kvm/book3s_xive.c t_vm_h_eoi += xc->stat_vm_h_eoi; xc 2127 arch/powerpc/kvm/book3s_xive.c t_vm_h_ipi += xc->stat_vm_h_ipi; xc 298 arch/powerpc/kvm/book3s_xive.h struct kvmppc_xive_vcpu *xc, int irq); xc 43 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 44 arch/powerpc/kvm/book3s_xive_native.c struct xive_q *q = &xc->queues[prio]; xc 46 arch/powerpc/kvm/book3s_xive_native.c xive_native_disable_queue(xc->vp_id, q, prio); xc 73 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 79 arch/powerpc/kvm/book3s_xive_native.c if (!xc) xc 82 arch/powerpc/kvm/book3s_xive_native.c pr_devel("native_cleanup_vcpu(cpu=%d)\n", xc->server_num); xc 85 arch/powerpc/kvm/book3s_xive_native.c xc->valid = false; xc 91 arch/powerpc/kvm/book3s_xive_native.c if (xc->esc_virq[i]) { xc 92 arch/powerpc/kvm/book3s_xive_native.c if (xc->xive->single_escalation) xc 93 arch/powerpc/kvm/book3s_xive_native.c xive_cleanup_single_escalation(vcpu, xc, xc 94 arch/powerpc/kvm/book3s_xive_native.c xc->esc_virq[i]); xc 95 arch/powerpc/kvm/book3s_xive_native.c free_irq(xc->esc_virq[i], vcpu); xc 96 arch/powerpc/kvm/book3s_xive_native.c irq_dispose_mapping(xc->esc_virq[i]); xc 97 arch/powerpc/kvm/book3s_xive_native.c kfree(xc->esc_virq_names[i]); xc 98 arch/powerpc/kvm/book3s_xive_native.c xc->esc_virq[i] = 0; xc 103 arch/powerpc/kvm/book3s_xive_native.c xive_native_disable_vp(xc->vp_id); xc 114 arch/powerpc/kvm/book3s_xive_native.c kfree(xc); xc 125 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc = NULL; xc 153 arch/powerpc/kvm/book3s_xive_native.c xc = kzalloc(sizeof(*xc), GFP_KERNEL); xc 154 arch/powerpc/kvm/book3s_xive_native.c if (!xc) { xc 159 arch/powerpc/kvm/book3s_xive_native.c vcpu->arch.xive_vcpu = xc; xc 160 arch/powerpc/kvm/book3s_xive_native.c xc->xive = xive; xc 161 arch/powerpc/kvm/book3s_xive_native.c xc->vcpu = vcpu; xc 162 arch/powerpc/kvm/book3s_xive_native.c xc->server_num = server_num; xc 164 arch/powerpc/kvm/book3s_xive_native.c xc->vp_id = vp_id; xc 165 arch/powerpc/kvm/book3s_xive_native.c xc->valid = true; xc 168 arch/powerpc/kvm/book3s_xive_native.c rc = xive_native_get_vp_info(xc->vp_id, &xc->vp_cam, &xc->vp_chip_id); xc 178 arch/powerpc/kvm/book3s_xive_native.c rc = xive_native_enable_vp(xc->vp_id, xive->single_escalation); xc 186 arch/powerpc/kvm/book3s_xive_native.c vcpu->arch.xive_cam_word = cpu_to_be32(xc->vp_cam | TM_QW1W2_VO); xc 556 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc; xc 585 arch/powerpc/kvm/book3s_xive_native.c xc = vcpu->arch.xive_vcpu; xc 592 arch/powerpc/kvm/book3s_xive_native.c q = &xc->queues[priority]; xc 603 arch/powerpc/kvm/book3s_xive_native.c rc = kvmppc_xive_native_configure_queue(xc->vp_id, q, priority, xc 607 arch/powerpc/kvm/book3s_xive_native.c priority, xc->server_num, rc); xc 670 arch/powerpc/kvm/book3s_xive_native.c rc = kvmppc_xive_native_configure_queue(xc->vp_id, q, priority, xc 674 arch/powerpc/kvm/book3s_xive_native.c priority, xc->server_num, rc); xc 684 arch/powerpc/kvm/book3s_xive_native.c rc = xive_native_set_queue_state(xc->vp_id, priority, xc 704 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc; xc 730 arch/powerpc/kvm/book3s_xive_native.c xc = vcpu->arch.xive_vcpu; xc 737 arch/powerpc/kvm/book3s_xive_native.c q = &xc->queues[priority]; xc 744 arch/powerpc/kvm/book3s_xive_native.c rc = xive_native_get_queue_info(xc->vp_id, priority, &qaddr, &qshift, xc 756 arch/powerpc/kvm/book3s_xive_native.c rc = xive_native_get_queue_state(xc->vp_id, priority, &kvm_eq.qtoggle, xc 808 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 811 arch/powerpc/kvm/book3s_xive_native.c if (!xc) xc 822 arch/powerpc/kvm/book3s_xive_native.c if (xc->esc_virq[prio]) { xc 823 arch/powerpc/kvm/book3s_xive_native.c free_irq(xc->esc_virq[prio], vcpu); xc 824 arch/powerpc/kvm/book3s_xive_native.c irq_dispose_mapping(xc->esc_virq[prio]); xc 825 arch/powerpc/kvm/book3s_xive_native.c kfree(xc->esc_virq_names[prio]); xc 826 arch/powerpc/kvm/book3s_xive_native.c xc->esc_virq[prio] = 0; xc 885 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 889 arch/powerpc/kvm/book3s_xive_native.c if (!xc) xc 893 arch/powerpc/kvm/book3s_xive_native.c struct xive_q *q = &xc->queues[prio]; xc 1130 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 1137 arch/powerpc/kvm/book3s_xive_native.c if (!xc) xc 1144 arch/powerpc/kvm/book3s_xive_native.c rc = xive_native_get_vp_state(xc->vp_id, &opal_state); xc 1168 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 1177 arch/powerpc/kvm/book3s_xive_native.c if (!xc || !xive) xc 1216 arch/powerpc/kvm/book3s_xive_native.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 1218 arch/powerpc/kvm/book3s_xive_native.c if (!xc) xc 1222 arch/powerpc/kvm/book3s_xive_native.c xc->server_num, xc 14 arch/powerpc/kvm/book3s_xive_template.c static void GLUE(X_PFX,ack_pending)(struct kvmppc_xive_vcpu *xc) xc 40 arch/powerpc/kvm/book3s_xive_template.c xc->pending |= 1 << cppr; xc 44 arch/powerpc/kvm/book3s_xive_template.c if (cppr >= xc->hw_cppr) xc 46 arch/powerpc/kvm/book3s_xive_template.c smp_processor_id(), cppr, xc->hw_cppr); xc 54 arch/powerpc/kvm/book3s_xive_template.c xc->hw_cppr = cppr; xc 112 arch/powerpc/kvm/book3s_xive_template.c static u32 GLUE(X_PFX,scan_interrupts)(struct kvmppc_xive_vcpu *xc, xc 119 arch/powerpc/kvm/book3s_xive_template.c while ((xc->mfrr != 0xff || pending != 0) && hirq == 0) { xc 131 arch/powerpc/kvm/book3s_xive_template.c if (prio >= xc->cppr || prio > 7) { xc 132 arch/powerpc/kvm/book3s_xive_template.c if (xc->mfrr < xc->cppr) { xc 133 arch/powerpc/kvm/book3s_xive_template.c prio = xc->mfrr; xc 140 arch/powerpc/kvm/book3s_xive_template.c q = &xc->queues[prio]; xc 175 arch/powerpc/kvm/book3s_xive_template.c GLUE(X_PFX,source_eoi)(xc->vp_ipi, xc 176 arch/powerpc/kvm/book3s_xive_template.c &xc->vp_ipi_data); xc 216 arch/powerpc/kvm/book3s_xive_template.c if (prio >= xc->mfrr && xc->mfrr < xc->cppr) { xc 217 arch/powerpc/kvm/book3s_xive_template.c prio = xc->mfrr; xc 234 arch/powerpc/kvm/book3s_xive_template.c xc->pending = pending; xc 254 arch/powerpc/kvm/book3s_xive_template.c xc->cppr = prio; xc 261 arch/powerpc/kvm/book3s_xive_template.c if (xc->cppr != xc->hw_cppr) { xc 262 arch/powerpc/kvm/book3s_xive_template.c xc->hw_cppr = xc->cppr; xc 263 arch/powerpc/kvm/book3s_xive_template.c __x_writeb(xc->cppr, __x_tima + TM_QW1_OS + TM_CPPR); xc 271 arch/powerpc/kvm/book3s_xive_template.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 277 arch/powerpc/kvm/book3s_xive_template.c xc->GLUE(X_STAT_PFX,h_xirr)++; xc 280 arch/powerpc/kvm/book3s_xive_template.c GLUE(X_PFX,ack_pending)(xc); xc 283 arch/powerpc/kvm/book3s_xive_template.c xc->pending, xc->hw_cppr, xc->cppr); xc 286 arch/powerpc/kvm/book3s_xive_template.c old_cppr = xive_prio_to_guest(xc->cppr); xc 289 arch/powerpc/kvm/book3s_xive_template.c hirq = GLUE(X_PFX,scan_interrupts)(xc, xc->pending, scan_fetch); xc 292 arch/powerpc/kvm/book3s_xive_template.c hirq, xc->hw_cppr, xc->cppr); xc 322 arch/powerpc/kvm/book3s_xive_template.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 323 arch/powerpc/kvm/book3s_xive_template.c u8 pending = xc->pending; xc 328 arch/powerpc/kvm/book3s_xive_template.c xc->GLUE(X_STAT_PFX,h_ipoll)++; xc 331 arch/powerpc/kvm/book3s_xive_template.c if (xc->server_num != server) { xc 335 arch/powerpc/kvm/book3s_xive_template.c xc = vcpu->arch.xive_vcpu; xc 347 arch/powerpc/kvm/book3s_xive_template.c hirq = GLUE(X_PFX,scan_interrupts)(xc, pending, scan_poll); xc 350 arch/powerpc/kvm/book3s_xive_template.c vcpu->arch.regs.gpr[4] = hirq | (xc->cppr << 24); xc 355 arch/powerpc/kvm/book3s_xive_template.c static void GLUE(X_PFX,push_pending_to_hw)(struct kvmppc_xive_vcpu *xc) xc 359 arch/powerpc/kvm/book3s_xive_template.c pending = xc->pending; xc 360 arch/powerpc/kvm/book3s_xive_template.c if (xc->mfrr != 0xff) { xc 361 arch/powerpc/kvm/book3s_xive_template.c if (xc->mfrr < 8) xc 362 arch/powerpc/kvm/book3s_xive_template.c pending |= 1 << xc->mfrr; xc 374 arch/powerpc/kvm/book3s_xive_template.c struct kvmppc_xive_vcpu *xc) xc 379 arch/powerpc/kvm/book3s_xive_template.c for (prio = xc->cppr; prio < KVMPPC_XIVE_Q_COUNT; prio++) { xc 380 arch/powerpc/kvm/book3s_xive_template.c struct xive_q *q = &xc->queues[prio]; xc 412 arch/powerpc/kvm/book3s_xive_template.c if (xc->server_num == state->act_server) xc 441 arch/powerpc/kvm/book3s_xive_template.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 447 arch/powerpc/kvm/book3s_xive_template.c xc->GLUE(X_STAT_PFX,h_cppr)++; xc 453 arch/powerpc/kvm/book3s_xive_template.c old_cppr = xc->cppr; xc 454 arch/powerpc/kvm/book3s_xive_template.c xc->cppr = cppr; xc 469 arch/powerpc/kvm/book3s_xive_template.c GLUE(X_PFX,push_pending_to_hw)(xc); xc 488 arch/powerpc/kvm/book3s_xive_template.c GLUE(X_PFX,scan_for_rerouted_irqs)(xive, xc); xc 492 arch/powerpc/kvm/book3s_xive_template.c xc->hw_cppr = cppr; xc 503 arch/powerpc/kvm/book3s_xive_template.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 512 arch/powerpc/kvm/book3s_xive_template.c xc->GLUE(X_STAT_PFX,h_eoi)++; xc 514 arch/powerpc/kvm/book3s_xive_template.c xc->cppr = xive_prio_from_guest(new_cppr); xc 592 arch/powerpc/kvm/book3s_xive_template.c GLUE(X_PFX,scan_interrupts)(xc, xc->pending, scan_eoi); xc 593 arch/powerpc/kvm/book3s_xive_template.c GLUE(X_PFX,push_pending_to_hw)(xc); xc 594 arch/powerpc/kvm/book3s_xive_template.c pr_devel(" after scan pending=%02x\n", xc->pending); xc 597 arch/powerpc/kvm/book3s_xive_template.c xc->hw_cppr = xc->cppr; xc 598 arch/powerpc/kvm/book3s_xive_template.c __x_writeb(xc->cppr, __x_tima + TM_QW1_OS + TM_CPPR); xc 606 arch/powerpc/kvm/book3s_xive_template.c struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu; xc 610 arch/powerpc/kvm/book3s_xive_template.c xc->GLUE(X_STAT_PFX,h_ipi)++; xc 616 arch/powerpc/kvm/book3s_xive_template.c xc = vcpu->arch.xive_vcpu; xc 619 arch/powerpc/kvm/book3s_xive_template.c xc->mfrr = mfrr; xc 634 arch/powerpc/kvm/book3s_xive_template.c if (mfrr < xc->cppr) xc 635 arch/powerpc/kvm/book3s_xive_template.c __x_writeq(0, __x_trig_page(&xc->vp_ipi_data)); xc 129 arch/powerpc/sysdev/xive/common.c static u32 xive_scan_interrupts(struct xive_cpu *xc, bool just_peek) xc 135 arch/powerpc/sysdev/xive/common.c while (xc->pending_prio != 0) { xc 138 arch/powerpc/sysdev/xive/common.c prio = ffs(xc->pending_prio) - 1; xc 142 arch/powerpc/sysdev/xive/common.c irq = xive_read_eq(&xc->queue[prio], just_peek); xc 160 arch/powerpc/sysdev/xive/common.c xc->pending_prio &= ~(1 << prio); xc 167 arch/powerpc/sysdev/xive/common.c q = &xc->queue[prio]; xc 182 arch/powerpc/sysdev/xive/common.c if (prio != xc->cppr) { xc 184 arch/powerpc/sysdev/xive/common.c xc->cppr = prio; xc 240 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = per_cpu(xive_cpu, cpu); xc 243 arch/powerpc/sysdev/xive/common.c if (xc) { xc 244 arch/powerpc/sysdev/xive/common.c xmon_printf("pp=%02x CPPR=%02x ", xc->pending_prio, xc->cppr); xc 248 arch/powerpc/sysdev/xive/common.c u64 val = xive_esb_read(&xc->ipi_data, XIVE_ESB_GET); xc 250 arch/powerpc/sysdev/xive/common.c xmon_printf("IPI=0x%08x PQ=%c%c ", xc->hw_ipi, xc 255 arch/powerpc/sysdev/xive/common.c xive_dump_eq("EQ", &xc->queue[xive_irq_priority]); xc 297 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = __this_cpu_read(xive_cpu); xc 314 arch/powerpc/sysdev/xive/common.c xive_ops->update_pending(xc); xc 316 arch/powerpc/sysdev/xive/common.c DBG_VERBOSE("get_irq: pending=%02x\n", xc->pending_prio); xc 319 arch/powerpc/sysdev/xive/common.c irq = xive_scan_interrupts(xc, false); xc 322 arch/powerpc/sysdev/xive/common.c irq, xc->pending_prio); xc 340 arch/powerpc/sysdev/xive/common.c static void xive_do_queue_eoi(struct xive_cpu *xc) xc 342 arch/powerpc/sysdev/xive/common.c if (xive_scan_interrupts(xc, true) != 0) { xc 343 arch/powerpc/sysdev/xive/common.c DBG_VERBOSE("eoi: pending=0x%02x\n", xc->pending_prio); xc 402 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = __this_cpu_read(xive_cpu); xc 405 arch/powerpc/sysdev/xive/common.c d->irq, irqd_to_hwirq(d), xc->pending_prio); xc 424 arch/powerpc/sysdev/xive/common.c xive_do_queue_eoi(xc); xc 466 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = per_cpu(xive_cpu, cpu); xc 467 arch/powerpc/sysdev/xive/common.c struct xive_q *q = &xc->queue[xive_irq_priority]; xc 490 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = per_cpu(xive_cpu, cpu); xc 491 arch/powerpc/sysdev/xive/common.c struct xive_q *q = &xc->queue[xive_irq_priority]; xc 493 arch/powerpc/sysdev/xive/common.c if (WARN_ON(cpu < 0 || !xc)) { xc 494 arch/powerpc/sysdev/xive/common.c pr_err("%s: cpu=%d xc=%p\n", __func__, cpu, xc); xc 571 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = per_cpu(xive_cpu, cpu); xc 572 arch/powerpc/sysdev/xive/common.c if (xc->chip_id == xd->src_chip) xc 1076 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc; xc 1079 arch/powerpc/sysdev/xive/common.c xc = per_cpu(xive_cpu, cpu); xc 1082 arch/powerpc/sysdev/xive/common.c smp_processor_id(), cpu, xc->hw_ipi); xc 1084 arch/powerpc/sysdev/xive/common.c xd = &xc->ipi_data; xc 1097 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = __this_cpu_read(xive_cpu); xc 1100 arch/powerpc/sysdev/xive/common.c if (!xc) xc 1104 arch/powerpc/sysdev/xive/common.c d->irq, irqd_to_hwirq(d), xc->hw_ipi, xc->pending_prio); xc 1106 arch/powerpc/sysdev/xive/common.c xive_do_source_eoi(xc->hw_ipi, &xc->ipi_data); xc 1107 arch/powerpc/sysdev/xive/common.c xive_do_queue_eoi(xc); xc 1147 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc; xc 1152 arch/powerpc/sysdev/xive/common.c xc = per_cpu(xive_cpu, cpu); xc 1155 arch/powerpc/sysdev/xive/common.c if (xc->hw_ipi != XIVE_BAD_IRQ) xc 1159 arch/powerpc/sysdev/xive/common.c if (xive_ops->get_ipi(cpu, xc)) xc 1166 arch/powerpc/sysdev/xive/common.c rc = xive_ops->populate_irq_data(xc->hw_ipi, &xc->ipi_data); xc 1171 arch/powerpc/sysdev/xive/common.c rc = xive_ops->configure_irq(xc->hw_ipi, xc 1179 arch/powerpc/sysdev/xive/common.c xc->hw_ipi, xive_ipi_irq, xc->ipi_data.trig_mmio); xc 1182 arch/powerpc/sysdev/xive/common.c xive_do_source_set_mask(&xc->ipi_data, false); xc 1187 arch/powerpc/sysdev/xive/common.c static void xive_cleanup_cpu_ipi(unsigned int cpu, struct xive_cpu *xc) xc 1192 arch/powerpc/sysdev/xive/common.c if (xc->hw_ipi == XIVE_BAD_IRQ) xc 1196 arch/powerpc/sysdev/xive/common.c xive_do_source_set_mask(&xc->ipi_data, true); xc 1205 arch/powerpc/sysdev/xive/common.c xive_ops->configure_irq(xc->hw_ipi, hard_smp_processor_id(), xc 1209 arch/powerpc/sysdev/xive/common.c xive_ops->put_ipi(cpu, xc); xc 1315 arch/powerpc/sysdev/xive/common.c static void xive_cleanup_cpu_queues(unsigned int cpu, struct xive_cpu *xc) xc 1317 arch/powerpc/sysdev/xive/common.c if (xc->queue[xive_irq_priority].qpage) xc 1318 arch/powerpc/sysdev/xive/common.c xive_ops->cleanup_queue(cpu, xc, xive_irq_priority); xc 1321 arch/powerpc/sysdev/xive/common.c static int xive_setup_cpu_queues(unsigned int cpu, struct xive_cpu *xc) xc 1326 arch/powerpc/sysdev/xive/common.c if (!xc->queue[xive_irq_priority].qpage) xc 1327 arch/powerpc/sysdev/xive/common.c rc = xive_ops->setup_queue(cpu, xc, xive_irq_priority); xc 1334 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc; xc 1336 arch/powerpc/sysdev/xive/common.c xc = per_cpu(xive_cpu, cpu); xc 1337 arch/powerpc/sysdev/xive/common.c if (!xc) { xc 1340 arch/powerpc/sysdev/xive/common.c xc = kzalloc_node(sizeof(struct xive_cpu), xc 1342 arch/powerpc/sysdev/xive/common.c if (!xc) xc 1346 arch/powerpc/sysdev/xive/common.c xc->chip_id = of_get_ibm_chip_id(np); xc 1348 arch/powerpc/sysdev/xive/common.c xc->hw_ipi = XIVE_BAD_IRQ; xc 1350 arch/powerpc/sysdev/xive/common.c per_cpu(xive_cpu, cpu) = xc; xc 1354 arch/powerpc/sysdev/xive/common.c return xive_setup_cpu_queues(cpu, xc); xc 1359 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = __this_cpu_read(xive_cpu); xc 1363 arch/powerpc/sysdev/xive/common.c xive_ops->setup_cpu(smp_processor_id(), xc); xc 1366 arch/powerpc/sysdev/xive/common.c xc->cppr = 0xff; xc 1395 arch/powerpc/sysdev/xive/common.c static void xive_flush_cpu_queue(unsigned int cpu, struct xive_cpu *xc) xc 1403 arch/powerpc/sysdev/xive/common.c while ((irq = xive_scan_interrupts(xc, false)) != 0) { xc 1452 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = __this_cpu_read(xive_cpu); xc 1459 arch/powerpc/sysdev/xive/common.c xc->cppr = 0; xc 1463 arch/powerpc/sysdev/xive/common.c xive_flush_cpu_queue(cpu, xc); xc 1466 arch/powerpc/sysdev/xive/common.c xc->cppr = 0xff; xc 1472 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = __this_cpu_read(xive_cpu); xc 1476 arch/powerpc/sysdev/xive/common.c xive_flush_cpu_queue(cpu, xc); xc 1485 arch/powerpc/sysdev/xive/common.c struct xive_cpu *xc = __this_cpu_read(xive_cpu); xc 1489 arch/powerpc/sysdev/xive/common.c xc->cppr = 0; xc 1493 arch/powerpc/sysdev/xive/common.c xive_ops->teardown_cpu(cpu, xc); xc 1497 arch/powerpc/sysdev/xive/common.c xive_cleanup_cpu_ipi(cpu, xc); xc 1501 arch/powerpc/sysdev/xive/common.c xive_cleanup_cpu_queues(cpu, xc); xc 215 arch/powerpc/sysdev/xive/native.c static int xive_native_setup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) xc 217 arch/powerpc/sysdev/xive/native.c struct xive_q *q = &xc->queue[prio]; xc 228 arch/powerpc/sysdev/xive/native.c static void xive_native_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, u8 prio) xc 230 arch/powerpc/sysdev/xive/native.c struct xive_q *q = &xc->queue[prio]; xc 260 arch/powerpc/sysdev/xive/native.c static int xive_native_get_ipi(unsigned int cpu, struct xive_cpu *xc) xc 266 arch/powerpc/sysdev/xive/native.c irq = opal_xive_allocate_irq(xc->chip_id); xc 275 arch/powerpc/sysdev/xive/native.c xc->hw_ipi = irq; xc 310 arch/powerpc/sysdev/xive/native.c static void xive_native_put_ipi(unsigned int cpu, struct xive_cpu *xc) xc 315 arch/powerpc/sysdev/xive/native.c if (xc->hw_ipi == XIVE_BAD_IRQ) xc 318 arch/powerpc/sysdev/xive/native.c rc = opal_xive_free_irq(xc->hw_ipi); xc 323 arch/powerpc/sysdev/xive/native.c xc->hw_ipi = XIVE_BAD_IRQ; xc 340 arch/powerpc/sysdev/xive/native.c static void xive_native_update_pending(struct xive_cpu *xc) xc 364 arch/powerpc/sysdev/xive/native.c xc->pending_prio |= 1 << cppr; xc 370 arch/powerpc/sysdev/xive/native.c if (cppr >= xc->cppr) xc 372 arch/powerpc/sysdev/xive/native.c smp_processor_id(), cppr, xc->cppr); xc 375 arch/powerpc/sysdev/xive/native.c xc->cppr = cppr; xc 394 arch/powerpc/sysdev/xive/native.c static void xive_native_setup_cpu(unsigned int cpu, struct xive_cpu *xc) xc 434 arch/powerpc/sysdev/xive/native.c static void xive_native_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) xc 509 arch/powerpc/sysdev/xive/spapr.c static int xive_spapr_setup_queue(unsigned int cpu, struct xive_cpu *xc, xc 512 arch/powerpc/sysdev/xive/spapr.c struct xive_q *q = &xc->queue[prio]; xc 523 arch/powerpc/sysdev/xive/spapr.c static void xive_spapr_cleanup_queue(unsigned int cpu, struct xive_cpu *xc, xc 526 arch/powerpc/sysdev/xive/spapr.c struct xive_q *q = &xc->queue[prio]; xc 548 arch/powerpc/sysdev/xive/spapr.c static int xive_spapr_get_ipi(unsigned int cpu, struct xive_cpu *xc) xc 557 arch/powerpc/sysdev/xive/spapr.c xc->hw_ipi = irq; xc 561 arch/powerpc/sysdev/xive/spapr.c static void xive_spapr_put_ipi(unsigned int cpu, struct xive_cpu *xc) xc 563 arch/powerpc/sysdev/xive/spapr.c if (xc->hw_ipi == XIVE_BAD_IRQ) xc 566 arch/powerpc/sysdev/xive/spapr.c xive_irq_bitmap_free(xc->hw_ipi); xc 567 arch/powerpc/sysdev/xive/spapr.c xc->hw_ipi = XIVE_BAD_IRQ; xc 580 arch/powerpc/sysdev/xive/spapr.c static void xive_spapr_update_pending(struct xive_cpu *xc) xc 608 arch/powerpc/sysdev/xive/spapr.c xc->pending_prio |= 1 << cppr; xc 614 arch/powerpc/sysdev/xive/spapr.c if (cppr >= xc->cppr) xc 616 arch/powerpc/sysdev/xive/spapr.c smp_processor_id(), cppr, xc->cppr); xc 619 arch/powerpc/sysdev/xive/spapr.c xc->cppr = cppr; xc 628 arch/powerpc/sysdev/xive/spapr.c static void xive_spapr_setup_cpu(unsigned int cpu, struct xive_cpu *xc) xc 637 arch/powerpc/sysdev/xive/spapr.c static void xive_spapr_teardown_cpu(unsigned int cpu, struct xive_cpu *xc) xc 45 arch/powerpc/sysdev/xive/xive-internal.h int (*setup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio); xc 46 arch/powerpc/sysdev/xive/xive-internal.h void (*cleanup_queue)(unsigned int cpu, struct xive_cpu *xc, u8 prio); xc 47 arch/powerpc/sysdev/xive/xive-internal.h void (*setup_cpu)(unsigned int cpu, struct xive_cpu *xc); xc 48 arch/powerpc/sysdev/xive/xive-internal.h void (*teardown_cpu)(unsigned int cpu, struct xive_cpu *xc); xc 52 arch/powerpc/sysdev/xive/xive-internal.h void (*update_pending)(struct xive_cpu *xc); xc 57 arch/powerpc/sysdev/xive/xive-internal.h int (*get_ipi)(unsigned int cpu, struct xive_cpu *xc); xc 58 arch/powerpc/sysdev/xive/xive-internal.h void (*put_ipi)(unsigned int cpu, struct xive_cpu *xc); xc 339 drivers/net/wan/lmc/lmc_main.c struct lmc_xilinx_control xc; /*fold02*/ xc 351 drivers/net/wan/lmc/lmc_main.c if (copy_from_user(&xc, ifr->ifr_data, sizeof(struct lmc_xilinx_control))) { xc 355 drivers/net/wan/lmc/lmc_main.c switch(xc.command){ xc 489 drivers/net/wan/lmc/lmc_main.c if (!xc.data) { xc 494 drivers/net/wan/lmc/lmc_main.c data = memdup_user(xc.data, xc.len); xc 500 drivers/net/wan/lmc/lmc_main.c printk("%s: Starting load of data Len: %d at 0x%p == 0x%p\n", dev->name, xc.len, xc.data, data); xc 559 drivers/net/wan/lmc/lmc_main.c for(pos = 0; pos < xc.len; pos++){ xc 2602 drivers/scsi/lpfc/lpfc_nvmet.c int xc = 1; xc 2645 drivers/scsi/lpfc/lpfc_nvmet.c xc = 0; /* create new XRI */ xc 2705 drivers/scsi/lpfc/lpfc_nvmet.c if (!xc) xc 2797 drivers/scsi/lpfc/lpfc_nvmet.c if (!xc) xc 2867 drivers/scsi/lpfc/lpfc_nvmet.c if (xc) xc 1444 drivers/staging/media/ipu3/ipu3-abi.h u16 xc; xc 4390 net/xfrm/xfrm_policy.c struct xfrm_state *x, *xc; xc 4415 net/xfrm/xfrm_policy.c xc = xfrm_state_migrate(x, mp, encap); xc 4416 net/xfrm/xfrm_policy.c if (xc) { xc 4417 net/xfrm/xfrm_policy.c x_new[nx_new] = xc; xc 1586 net/xfrm/xfrm_state.c struct xfrm_state *xc; xc 1588 net/xfrm/xfrm_state.c xc = xfrm_state_clone(x, encap); xc 1589 net/xfrm/xfrm_state.c if (!xc) xc 1592 net/xfrm/xfrm_state.c memcpy(&xc->id.daddr, &m->new_daddr, sizeof(xc->id.daddr)); xc 1593 net/xfrm/xfrm_state.c memcpy(&xc->props.saddr, &m->new_saddr, sizeof(xc->props.saddr)); xc 1599 net/xfrm/xfrm_state.c xfrm_state_insert(xc); xc 1601 net/xfrm/xfrm_state.c if (xfrm_state_add(xc) < 0) xc 1605 net/xfrm/xfrm_state.c return xc; xc 1607 net/xfrm/xfrm_state.c xfrm_state_put(xc);