CNVC_SURFACE_PIXEL_FORMAT  397 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
CNVC_SURFACE_PIXEL_FORMAT  398 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c 			CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
CNVC_SURFACE_PIXEL_FORMAT  118 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
CNVC_SURFACE_PIXEL_FORMAT  322 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	TF_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
CNVC_SURFACE_PIXEL_FORMAT 1065 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	type CNVC_SURFACE_PIXEL_FORMAT; \
CNVC_SURFACE_PIXEL_FORMAT 1331 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h 	uint32_t CNVC_SURFACE_PIXEL_FORMAT; \
CNVC_SURFACE_PIXEL_FORMAT  722 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
CNVC_SURFACE_PIXEL_FORMAT  723 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_cm.c 			CNVC_SURFACE_PIXEL_FORMAT, 0x8);
CNVC_SURFACE_PIXEL_FORMAT   36 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
CNVC_SURFACE_PIXEL_FORMAT   78 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	IPP_SF(CNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT, CNVC_SURFACE_PIXEL_FORMAT, mask_sh), \
CNVC_SURFACE_PIXEL_FORMAT  130 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	type CNVC_SURFACE_PIXEL_FORMAT; \
CNVC_SURFACE_PIXEL_FORMAT  168 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h 	uint32_t CNVC_SURFACE_PIXEL_FORMAT;
CNVC_SURFACE_PIXEL_FORMAT  217 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 	REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
CNVC_SURFACE_PIXEL_FORMAT  218 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.c 			CNVC_SURFACE_PIXEL_FORMAT, pixel_format);