x86_clflush_size  111 arch/x86/include/asm/processor.h 	u16			x86_clflush_size;
x86_clflush_size   71 arch/x86/kernel/cpu/centaur.c 		c->x86_cache_alignment = c->x86_clflush_size * 2;
x86_clflush_size  818 arch/x86/kernel/cpu/common.c 			c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
x86_clflush_size  819 arch/x86/kernel/cpu/common.c 			c->x86_cache_alignment = c->x86_clflush_size;
x86_clflush_size 1238 arch/x86/kernel/cpu/common.c 	c->x86_clflush_size = 64;
x86_clflush_size 1242 arch/x86/kernel/cpu/common.c 	c->x86_clflush_size = 32;
x86_clflush_size 1246 arch/x86/kernel/cpu/common.c 	c->x86_cache_alignment = c->x86_clflush_size;
x86_clflush_size 1482 arch/x86/kernel/cpu/common.c 	c->x86_clflush_size = 64;
x86_clflush_size 1487 arch/x86/kernel/cpu/common.c 	c->x86_clflush_size = 32;
x86_clflush_size 1491 arch/x86/kernel/cpu/common.c 	c->x86_cache_alignment = c->x86_clflush_size;
x86_clflush_size  711 arch/x86/kernel/cpu/intel.c 		c->x86_cache_alignment = c->x86_clflush_size * 2;
x86_clflush_size  121 arch/x86/kernel/cpu/proc.c 	seq_printf(m, "clflush size\t: %u\n", c->x86_clflush_size);
x86_clflush_size   91 arch/x86/lib/usercopy_64.c 	u16 x86_clflush_size = boot_cpu_data.x86_clflush_size;
x86_clflush_size   92 arch/x86/lib/usercopy_64.c 	unsigned long clflush_mask = x86_clflush_size - 1;
x86_clflush_size   97 arch/x86/lib/usercopy_64.c 	     p < vend; p += x86_clflush_size)
x86_clflush_size  125 arch/x86/lib/usercopy_64.c 			dest = ALIGN(dest, boot_cpu_data.x86_clflush_size);
x86_clflush_size  281 arch/x86/mm/pageattr.c 	const unsigned long clflush_size = boot_cpu_data.x86_clflush_size;
x86_clflush_size  490 arch/x86/pci/common.c 	if (c->x86_clflush_size > 0) {
x86_clflush_size  491 arch/x86/pci/common.c 		pci_dfl_cache_line_size = c->x86_clflush_size >> 2;
x86_clflush_size   49 drivers/gpu/drm/drm_cache.c 	const int size = boot_cpu_data.x86_clflush_size;
x86_clflush_size  158 drivers/gpu/drm/drm_cache.c 		const int size = boot_cpu_data.x86_clflush_size;
x86_clflush_size 1180 drivers/gpu/drm/i915/i915_cmd_parser.c 					    boot_cpu_data.x86_clflush_size);
x86_clflush_size  706 drivers/gpu/drm/i915/i915_gem.c 		partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1;