CNVC_CUR0_CURSOR0_CONTROL 323 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ CNVC_CUR0_CURSOR0_CONTROL 324 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ CNVC_CUR0_CURSOR0_CONTROL 325 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh), \ CNVC_CUR0_CURSOR0_CONTROL 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_MODE, mask_sh), \ CNVC_CUR0_CURSOR0_CONTROL 85 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_EXPANSION_MODE, mask_sh), \ CNVC_CUR0_CURSOR0_CONTROL 86 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ENABLE, mask_sh) CNVC_CUR0_CURSOR0_CONTROL 557 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIX_INV_MODE, mask_sh), \ CNVC_CUR0_CURSOR0_CONTROL 558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_PIXEL_ALPHA_MOD_EN, mask_sh), \ CNVC_CUR0_CURSOR0_CONTROL 559 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CUR0_CURSOR0_CONTROL, CUR0_ROM_EN, mask_sh),\