CNVC_CFG0_FORMAT_CONTROL 319 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ CNVC_CFG0_FORMAT_CONTROL 321 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ CNVC_CFG0_FORMAT_CONTROL 430 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh), \ CNVC_CFG0_FORMAT_CONTROL 79 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS, mask_sh), \ CNVC_CFG0_FORMAT_CONTROL 80 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CFG0_FORMAT_CONTROL, ALPHA_EN, mask_sh), \ CNVC_CFG0_FORMAT_CONTROL 81 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_EXPANSION_MODE, mask_sh), \ CNVC_CFG0_FORMAT_CONTROL 106 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_ipp.h IPP_SF(CNVC_CFG0_FORMAT_CONTROL, OUTPUT_FP, mask_sh) CNVC_CFG0_FORMAT_CONTROL 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, FORMAT_CNV16, mask_sh), \ CNVC_CFG0_FORMAT_CONTROL 534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, mask_sh), \ CNVC_CFG0_FORMAT_CONTROL 535 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE, mask_sh), \ CNVC_CFG0_FORMAT_CONTROL 536 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dpp.h TF_SF(CNVC_CFG0_FORMAT_CONTROL, CLAMP_POSITIVE_C, mask_sh), \