wrpll 1233 drivers/gpu/drm/i915/display/intel_ddi.c u32 wrpll; wrpll 1235 drivers/gpu/drm/i915/display/intel_ddi.c wrpll = I915_READ(reg); wrpll 1236 drivers/gpu/drm/i915/display/intel_ddi.c switch (wrpll & WRPLL_REF_MASK) { wrpll 1263 drivers/gpu/drm/i915/display/intel_ddi.c MISSING_CASE(wrpll); wrpll 1267 drivers/gpu/drm/i915/display/intel_ddi.c r = wrpll & WRPLL_DIVIDER_REF_MASK; wrpll 1268 drivers/gpu/drm/i915/display/intel_ddi.c p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; wrpll 1269 drivers/gpu/drm/i915/display/intel_ddi.c n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; wrpll 12799 drivers/gpu/drm/i915/display/intel_display.c PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); wrpll 506 drivers/gpu/drm/i915/display/intel_dpll_mgr.c I915_WRITE(WRPLL_CTL(id), pll->state.hw_state.wrpll); wrpll 569 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->wrpll = val; wrpll 828 drivers/gpu/drm/i915/display/intel_dpll_mgr.c crtc_state->dpll_hw_state.wrpll = val; wrpll 915 drivers/gpu/drm/i915/display/intel_dpll_mgr.c hw_state->wrpll, hw_state->spll); wrpll 2465 drivers/gpu/drm/i915/display/intel_dpll_mgr.c struct skl_wrpll_params wrpll; wrpll 2551 drivers/gpu/drm/i915/display/intel_dpll_mgr.c *pll_params = params[i].wrpll; wrpll 176 drivers/gpu/drm/i915/display/intel_dpll_mgr.h u32 wrpll; wrpll 2844 drivers/gpu/drm/i915/i915_debugfs.c seq_printf(m, " wrpll: 0x%08x\n", pll->state.hw_state.wrpll);