write_val2 368 drivers/phy/cadence/phy-cadence-dp.c u32 write_val2 = 0; write_val2 388 drivers/phy/cadence/phy-cadence-dp.c write_val2 = 0x00000001; write_val2 393 drivers/phy/cadence/phy-cadence-dp.c write_val2 = 0x00000101; write_val2 398 drivers/phy/cadence/phy-cadence-dp.c write_val2 = 0x01010101; write_val2 415 drivers/phy/cadence/phy-cadence-dp.c writel(write_val2, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); write_val2 418 drivers/phy/cadence/phy-cadence-dp.c read_val, (read_val & mask) == write_val2, 0,