write_val1 367 drivers/phy/cadence/phy-cadence-dp.c u32 write_val1 = 0; write_val1 387 drivers/phy/cadence/phy-cadence-dp.c write_val1 = 0x00000004; write_val1 392 drivers/phy/cadence/phy-cadence-dp.c write_val1 = 0x00000404; write_val1 397 drivers/phy/cadence/phy-cadence-dp.c write_val1 = 0x04040404; write_val1 403 drivers/phy/cadence/phy-cadence-dp.c writel(write_val1, cdns_phy->base + PHY_PMA_XCVR_POWER_STATE_REQ); write_val1 406 drivers/phy/cadence/phy-cadence-dp.c read_val, (read_val & mask) == write_val1, 0,