wr_buffers         49 drivers/char/xillybus/xillybus.h 	struct xilly_buffer **wr_buffers; /* FPGA writes, driver reads! */
wr_buffers        199 drivers/char/xillybus/xillybus_core.c 				channel->wr_buffers[msg_bufno]->end_offset =
wr_buffers        447 drivers/char/xillybus/xillybus_core.c 		channel->wr_buffers = NULL;
wr_buffers        543 drivers/char/xillybus/xillybus_core.c 			channel->wr_buffers = buffers;
wr_buffers        568 drivers/char/xillybus/xillybus_core.c 	unsigned char *idt = endpoint->channels[1]->wr_buffers[0]->addr;
wr_buffers        636 drivers/char/xillybus/xillybus_core.c 		channel->wr_buffers[0]->dma_addr,
wr_buffers        640 drivers/char/xillybus/xillybus_core.c 	if (channel->wr_buffers[0]->end_offset != endpoint->idtlen) {
wr_buffers        643 drivers/char/xillybus/xillybus_core.c 			channel->wr_buffers[0]->end_offset, endpoint->idtlen);
wr_buffers        647 drivers/char/xillybus/xillybus_core.c 	if (crc32_le(~0, channel->wr_buffers[0]->addr,
wr_buffers        653 drivers/char/xillybus/xillybus_core.c 	version = channel->wr_buffers[0]->addr;
wr_buffers        702 drivers/char/xillybus/xillybus_core.c 			howmany = ((channel->wr_buffers[bufidx]->end_offset
wr_buffers        751 drivers/char/xillybus/xillybus_core.c 					channel->wr_buffers[bufidx]->dma_addr,
wr_buffers        757 drivers/char/xillybus/xillybus_core.c 				    channel->wr_buffers[bufidx]->addr
wr_buffers        767 drivers/char/xillybus/xillybus_core.c 					channel->wr_buffers[bufidx]->dma_addr,