wptr 182 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h #define read_user_wptr(mmptr, wptr, dst) \ wptr 185 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h if ((mmptr) && (wptr)) { \ wptr 187 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h valid = !get_user((dst), (wptr)); \ wptr 190 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h valid = !get_user((dst), (wptr)); \ wptr 131 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint32_t __user *wptr, struct mm_struct *mm) wptr 139 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c uint64_t __user *wptr64 = (uint64_t __user *)wptr; wptr 65 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t queue_id, uint32_t __user *wptr, wptr 72 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t __user *wptr, struct mm_struct *mm); wptr 358 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t queue_id, uint32_t __user *wptr, wptr 401 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c if (wptr) { wptr 433 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c lower_32_bits((uint64_t)wptr)); wptr 435 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c upper_32_bits((uint64_t)wptr)); wptr 487 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint32_t __user *wptr, struct mm_struct *mm) wptr 495 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.c uint64_t __user *wptr64 = (uint64_t __user *)wptr; wptr 102 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t queue_id, uint32_t __user *wptr, wptr 109 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t __user *wptr, struct mm_struct *mm); wptr 329 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t queue_id, uint32_t __user *wptr, wptr 361 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c valid_wptr = read_user_wptr(mm, wptr, wptr_val); wptr 411 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c uint32_t __user *wptr, struct mm_struct *mm) wptr 451 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.c if (read_user_wptr(mm, wptr, data)) wptr 59 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t queue_id, uint32_t __user *wptr, wptr 66 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t __user *wptr, struct mm_struct *mm); wptr 285 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t queue_id, uint32_t __user *wptr, wptr 346 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c valid_wptr = read_user_wptr(mm, wptr, wptr_val); wptr 396 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c uint32_t __user *wptr, struct mm_struct *mm) wptr 435 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.c if (read_user_wptr(mm, wptr, data)) wptr 260 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t queue_id, uint32_t __user *wptr, wptr 302 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c if (wptr) { wptr 334 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c lower_32_bits((uintptr_t)wptr)); wptr 336 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c upper_32_bits((uintptr_t)wptr)); wptr 387 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint32_t __user *wptr, struct mm_struct *mm) wptr 395 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c uint64_t __user *wptr64 = (uint64_t __user *)wptr; wptr 33 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h uint32_t queue_id, uint32_t __user *wptr, wptr 147 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c u32 wptr; wptr 152 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c wptr = amdgpu_ih_get_wptr(adev, ih); wptr 159 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c DRM_DEBUG("%s: rptr %d, wptr %d\n", __func__, ih->rptr, wptr); wptr 164 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c while (ih->rptr != wptr && --count) { wptr 173 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c wptr = amdgpu_ih_get_wptr(adev, ih); wptr 174 drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c if (wptr != ih->rptr) wptr 1010 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c while (data->rptr != data->wptr) { wptr 1063 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c memcpy(&data->ring[data->wptr], info->entry, wptr 1067 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c data->wptr = (data->aligned_element_size + wptr 1068 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c data->wptr) % data->ring_size; wptr 1118 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c .wptr = 0, wptr 383 drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h unsigned int wptr; wptr 78 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c ring->wptr_old = ring->wptr; wptr 130 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c (ring->wptr & ring->funcs->align_mask); wptr 150 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c ring->wptr = ring->wptr_old; wptr 451 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c early[2] = ring->wptr & ring->buf_mask; wptr 187 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h u64 wptr; wptr 293 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h ring->ring[ring->wptr++ & ring->buf_mask] = v; wptr 294 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h ring->wptr &= ring->ptr_mask; wptr 307 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h occupied = ring->wptr & ring->buf_mask; wptr 324 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h ring->wptr += count_dw; wptr 325 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h ring->wptr &= ring->ptr_mask; wptr 190 drivers/gpu/drm/amd/amdgpu/cik_ih.c u32 wptr, tmp; wptr 192 drivers/gpu/drm/amd/amdgpu/cik_ih.c wptr = le32_to_cpu(*ih->wptr_cpu); wptr 194 drivers/gpu/drm/amd/amdgpu/cik_ih.c if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { wptr 195 drivers/gpu/drm/amd/amdgpu/cik_ih.c wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; wptr 201 drivers/gpu/drm/amd/amdgpu/cik_ih.c wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); wptr 202 drivers/gpu/drm/amd/amdgpu/cik_ih.c ih->rptr = (wptr + 16) & ih->ptr_mask; wptr 207 drivers/gpu/drm/amd/amdgpu/cik_ih.c return (wptr & ih->ptr_mask); wptr 198 drivers/gpu/drm/amd/amdgpu/cik_sdma.c (lower_32_bits(ring->wptr) << 2) & 0x3fffc); wptr 231 drivers/gpu/drm/amd/amdgpu/cik_sdma.c cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7); wptr 487 drivers/gpu/drm/amd/amdgpu/cik_sdma.c ring->wptr = 0; wptr 488 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); wptr 192 drivers/gpu/drm/amd/amdgpu/cz_ih.c u32 wptr, tmp; wptr 194 drivers/gpu/drm/amd/amdgpu/cz_ih.c wptr = le32_to_cpu(*ih->wptr_cpu); wptr 196 drivers/gpu/drm/amd/amdgpu/cz_ih.c if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { wptr 197 drivers/gpu/drm/amd/amdgpu/cz_ih.c wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); wptr 203 drivers/gpu/drm/amd/amdgpu/cz_ih.c wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); wptr 204 drivers/gpu/drm/amd/amdgpu/cz_ih.c ih->rptr = (wptr + 16) & ih->ptr_mask; wptr 209 drivers/gpu/drm/amd/amdgpu/cz_ih.c return (wptr & ih->ptr_mask); wptr 2840 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ring->wptr = 0; wptr 2841 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); wptr 2842 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); wptr 2877 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ring->wptr = 0; wptr 2878 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); wptr 2879 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr)); wptr 3096 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ring->wptr = 0; wptr 3176 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ring->wptr = 0; wptr 3306 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ring->wptr = 0; wptr 3370 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ring->wptr = 0; wptr 3511 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ring->wptr = 0; wptr 3557 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ring->wptr = 0; wptr 4366 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u64 wptr; wptr 4370 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); wptr 4372 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); wptr 4373 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; wptr 4376 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c return wptr; wptr 4385 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); wptr 4386 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WDOORBELL64(ring->doorbell_index, ring->wptr); wptr 4388 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); wptr 4389 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); wptr 4400 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c u64 wptr; wptr 4404 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); wptr 4407 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c return wptr; wptr 4416 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr); wptr 4417 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c WDOORBELL64(ring->doorbell_index, ring->wptr); wptr 4661 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c ret = ring->wptr & ring->buf_mask; wptr 4673 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c cur = (ring->wptr - 1) & ring->buf_mask; wptr 2120 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ring->wptr = 0; wptr 2121 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_WPTR, ring->wptr); wptr 2167 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); wptr 2176 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_WPTR, lower_32_bits(ring->wptr)); wptr 2179 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); wptr 2207 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ring->wptr = 0; wptr 2208 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB1_WPTR, ring->wptr); wptr 2227 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c ring->wptr = 0; wptr 2228 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c WREG32(mmCP_RB2_WPTR, ring->wptr); wptr 2631 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ring->wptr = 0; wptr 2632 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); wptr 2674 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); wptr 2689 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 2690 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 3019 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c ring->wptr = 0; wptr 3020 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c mqd->cp_hqd_pq_wptr = lower_32_bits(ring->wptr); wptr 4318 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ring->wptr = 0; wptr 4319 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); wptr 4552 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ring->wptr = 0; wptr 4553 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c mqd->cp_hqd_pq_wptr = ring->wptr; wptr 4651 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ring->wptr = 0; wptr 4699 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ring->wptr = 0; wptr 6063 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 6064 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 6066 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); wptr 6271 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 6272 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 6466 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c ret = ring->wptr & ring->buf_mask; wptr 6478 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c cur = (ring->wptr & ring->buf_mask) - 1; wptr 3223 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ring->wptr = 0; wptr 3224 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); wptr 3225 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); wptr 3467 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ring->wptr = 0; wptr 3531 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ring->wptr = 0; wptr 3710 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ring->wptr = 0; wptr 3760 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ring->wptr = 0; wptr 4250 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c if (ring->wptr == gfx_v9_0_ring_get_rptr_compute(ring)) wptr 4955 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u64 wptr; wptr 4959 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]); wptr 4961 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); wptr 4962 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32; wptr 4965 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c return wptr; wptr 4974 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); wptr 4975 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WDOORBELL64(ring->doorbell_index, ring->wptr); wptr 4977 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); wptr 4978 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr)); wptr 5144 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c u64 wptr; wptr 5148 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]); wptr 5151 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c return wptr; wptr 5259 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr); wptr 5260 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c WDOORBELL64(ring->doorbell_index, ring->wptr); wptr 5387 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c ret = ring->wptr & ring->buf_mask; wptr 5398 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c cur = (ring->wptr & ring->buf_mask) - 1; wptr 192 drivers/gpu/drm/amd/amdgpu/iceland_ih.c u32 wptr, tmp; wptr 194 drivers/gpu/drm/amd/amdgpu/iceland_ih.c wptr = le32_to_cpu(*ih->wptr_cpu); wptr 196 drivers/gpu/drm/amd/amdgpu/iceland_ih.c if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { wptr 197 drivers/gpu/drm/amd/amdgpu/iceland_ih.c wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); wptr 203 drivers/gpu/drm/amd/amdgpu/iceland_ih.c wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); wptr 204 drivers/gpu/drm/amd/amdgpu/iceland_ih.c ih->rptr = (wptr + 16) & ih->ptr_mask; wptr 209 drivers/gpu/drm/amd/amdgpu/iceland_ih.c return (wptr & ih->ptr_mask); wptr 213 drivers/gpu/drm/amd/amdgpu/navi10_ih.c u32 wptr, reg, tmp; wptr 215 drivers/gpu/drm/amd/amdgpu/navi10_ih.c wptr = le32_to_cpu(*ih->wptr_cpu); wptr 217 drivers/gpu/drm/amd/amdgpu/navi10_ih.c if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) wptr 221 drivers/gpu/drm/amd/amdgpu/navi10_ih.c wptr = RREG32_NO_KIQ(reg); wptr 222 drivers/gpu/drm/amd/amdgpu/navi10_ih.c if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) wptr 224 drivers/gpu/drm/amd/amdgpu/navi10_ih.c wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); wptr 230 drivers/gpu/drm/amd/amdgpu/navi10_ih.c tmp = (wptr + 32) & ih->ptr_mask; wptr 233 drivers/gpu/drm/amd/amdgpu/navi10_ih.c wptr, ih->rptr, tmp); wptr 241 drivers/gpu/drm/amd/amdgpu/navi10_ih.c return (wptr & ih->ptr_mask); wptr 210 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; wptr 212 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c return wptr; wptr 226 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); wptr 258 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); wptr 465 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c ring->wptr = 0; wptr 466 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); wptr 366 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c u32 wptr; wptr 370 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c wptr = ring->adev->wb.wb[ring->wptr_offs] >> 2; wptr 372 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2; wptr 375 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c return wptr; wptr 392 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); wptr 393 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); wptr 397 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); wptr 399 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); wptr 432 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); wptr 687 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c ring->wptr = 0; wptr 562 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c u64 wptr; wptr 566 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); wptr 567 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", wptr); wptr 569 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); wptr 570 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c wptr = wptr << 32; wptr 571 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c wptr |= RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR); wptr 573 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ring->me, wptr); wptr 576 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return wptr >> 2; wptr 599 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c lower_32_bits(ring->wptr << 2), wptr 600 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(ring->wptr << 2)); wptr 602 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WRITE_ONCE(*wb, (ring->wptr << 2)); wptr 604 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ring->doorbell_index, ring->wptr << 2); wptr 605 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WDOORBELL64(ring->doorbell_index, ring->wptr << 2); wptr 611 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c lower_32_bits(ring->wptr << 2), wptr 613 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(ring->wptr << 2)); wptr 615 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c lower_32_bits(ring->wptr << 2)); wptr 617 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(ring->wptr << 2)); wptr 631 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c u64 wptr; wptr 635 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c wptr = READ_ONCE(*((u64 *)&adev->wb.wb[ring->wptr_offs])); wptr 637 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c wptr = RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR_HI); wptr 638 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c wptr = wptr << 32; wptr 639 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c wptr |= RREG32_SDMA(ring->me, mmSDMA0_PAGE_RB_WPTR); wptr 642 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return wptr >> 2; wptr 660 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WRITE_ONCE(*wb, (ring->wptr << 2)); wptr 661 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WDOORBELL64(ring->doorbell_index, ring->wptr << 2); wptr 663 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c uint64_t wptr = ring->wptr << 2; wptr 666 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c lower_32_bits(wptr)); wptr 668 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c upper_32_bits(wptr)); wptr 701 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); wptr 1016 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ring->wptr = 0; wptr 1106 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c ring->wptr = 0; wptr 240 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ret = ring->wptr & ring->buf_mask;/* this is the offset we need patch later */ wptr 254 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c cur = (ring->wptr - 1) & ring->buf_mask; wptr 289 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c u64 *wptr = NULL; wptr 294 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c wptr = ((u64 *)&adev->wb.wb[ring->wptr_offs]); wptr 295 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c DRM_DEBUG("wptr/doorbell before shift == 0x%016llx\n", *wptr); wptr 296 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c *wptr = (*wptr) >> 2; wptr 297 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c DRM_DEBUG("wptr/doorbell after shift == 0x%016llx\n", *wptr); wptr 301 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c wptr = &local_wptr; wptr 307 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c *wptr = highbit; wptr 308 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c *wptr = (*wptr) << 32; wptr 309 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c *wptr |= lowbit; wptr 312 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c return *wptr; wptr 333 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c lower_32_bits(ring->wptr << 2), wptr 334 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c upper_32_bits(ring->wptr << 2)); wptr 336 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); wptr 337 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); wptr 339 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ring->doorbell_index, ring->wptr << 2); wptr 340 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WDOORBELL64(ring->doorbell_index, ring->wptr << 2); wptr 346 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c lower_32_bits(ring->wptr << 2), wptr 348 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c upper_32_bits(ring->wptr << 2)); wptr 350 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c lower_32_bits(ring->wptr << 2)); wptr 352 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c upper_32_bits(ring->wptr << 2)); wptr 405 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); wptr 682 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c ring->wptr = 0; wptr 688 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr) << 2); wptr 689 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); wptr 60 drivers/gpu/drm/amd/amdgpu/si_dma.c (lower_32_bits(ring->wptr) << 2) & 0x3fffc); wptr 72 drivers/gpu/drm/amd/amdgpu/si_dma.c while ((lower_32_bits(ring->wptr) & 7) != 5) wptr 176 drivers/gpu/drm/amd/amdgpu/si_dma.c ring->wptr = 0; wptr 177 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); wptr 108 drivers/gpu/drm/amd/amdgpu/si_ih.c u32 wptr, tmp; wptr 110 drivers/gpu/drm/amd/amdgpu/si_ih.c wptr = le32_to_cpu(*ih->wptr_cpu); wptr 112 drivers/gpu/drm/amd/amdgpu/si_ih.c if (wptr & IH_RB_WPTR__RB_OVERFLOW_MASK) { wptr 113 drivers/gpu/drm/amd/amdgpu/si_ih.c wptr &= ~IH_RB_WPTR__RB_OVERFLOW_MASK; wptr 115 drivers/gpu/drm/amd/amdgpu/si_ih.c wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); wptr 116 drivers/gpu/drm/amd/amdgpu/si_ih.c ih->rptr = (wptr + 16) & ih->ptr_mask; wptr 121 drivers/gpu/drm/amd/amdgpu/si_ih.c return (wptr & ih->ptr_mask); wptr 194 drivers/gpu/drm/amd/amdgpu/tonga_ih.c u32 wptr, tmp; wptr 196 drivers/gpu/drm/amd/amdgpu/tonga_ih.c wptr = le32_to_cpu(*ih->wptr_cpu); wptr 198 drivers/gpu/drm/amd/amdgpu/tonga_ih.c if (REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) { wptr 199 drivers/gpu/drm/amd/amdgpu/tonga_ih.c wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); wptr 205 drivers/gpu/drm/amd/amdgpu/tonga_ih.c wptr, ih->rptr, (wptr + 16) & ih->ptr_mask); wptr 206 drivers/gpu/drm/amd/amdgpu/tonga_ih.c ih->rptr = (wptr + 16) & ih->ptr_mask; wptr 211 drivers/gpu/drm/amd/amdgpu/tonga_ih.c return (wptr & ih->ptr_mask); wptr 90 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 360 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); wptr 361 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 526 drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c WARN_ON(ring->wptr % 2 || count % 2); wptr 88 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 418 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); wptr 419 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 544 drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c WARN_ON(ring->wptr % 2 || count % 2); wptr 142 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 158 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c lower_32_bits(ring->wptr)); wptr 161 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c lower_32_bits(ring->wptr)); wptr 835 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c ring->wptr = RREG32(mmUVD_RBC_RB_RPTR); wptr 836 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 842 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); wptr 843 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); wptr 849 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); wptr 850 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 1078 drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c WARN_ON(ring->wptr % 2 || count % 2); wptr 140 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 156 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 157 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 163 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c lower_32_bits(ring->wptr)); wptr 166 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c lower_32_bits(ring->wptr)); wptr 740 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c adev->uvd.inst[i].ring_enc[0].wptr = 0; wptr 797 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring->wptr = 0; wptr 900 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring->wptr = 0; wptr 1086 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR); wptr 1088 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c lower_32_bits(ring->wptr)); wptr 1094 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); wptr 1095 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); wptr 1101 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); wptr 1102 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 1390 drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c WARN_ON(ring->wptr % 2 || count % 2); wptr 94 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); wptr 96 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 244 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); wptr 245 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); wptr 251 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); wptr 252 drivers/gpu/drm/amd/amdgpu/vce_v2_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 153 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); wptr 155 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 157 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); wptr 281 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); wptr 282 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); wptr 288 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); wptr 289 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 295 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); wptr 296 drivers/gpu/drm/amd/amdgpu/vce_v3_0.c WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); wptr 108 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 109 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 115 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c lower_32_bits(ring->wptr)); wptr 118 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c lower_32_bits(ring->wptr)); wptr 121 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c lower_32_bits(ring->wptr)); wptr 180 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c adev->vce.ring[0].wptr = 0; wptr 342 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); wptr 343 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); wptr 350 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); wptr 351 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR2), lower_32_bits(ring->wptr)); wptr 358 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR3), lower_32_bits(ring->wptr)); wptr 359 drivers/gpu/drm/amd/amdgpu/vce_v4_0.c WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR3), lower_32_bits(ring->wptr)); wptr 930 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); wptr 932 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c lower_32_bits(ring->wptr)); wptr 938 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); wptr 939 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); wptr 945 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); wptr 946 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 962 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); wptr 966 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); wptr 1103 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); wptr 1105 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c lower_32_bits(ring->wptr)); wptr 1112 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); wptr 1116 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c (ring->wptr + ring->max_dw * amdgpu_sched_hw_submission)); wptr 1264 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); wptr 1265 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); wptr 1271 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); wptr 1272 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 1329 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); wptr 1330 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); wptr 1429 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c lower_32_bits(ring->wptr) | 0x80000000); wptr 1431 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 1637 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c lower_32_bits(ring->wptr)); wptr 1640 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c lower_32_bits(ring->wptr)); wptr 1760 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 2004 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WARN_ON(ring->wptr % 2 || count % 2); wptr 2144 drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c WARN_ON(ring->wptr % 2 || count % 2); wptr 723 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR); wptr 1047 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); wptr 1049 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c lower_32_bits(ring->wptr)); wptr 1203 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR); wptr 1205 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c lower_32_bits(ring->wptr)); wptr 1208 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); wptr 1209 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); wptr 1215 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); wptr 1216 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 1365 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); wptr 1366 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); wptr 1372 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); wptr 1373 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 1473 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c lower_32_bits(ring->wptr) | 0x80000000); wptr 1476 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 1477 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 1479 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 1527 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WARN_ON(ring->wptr % 2 || count % 2); wptr 1703 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 1704 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 1706 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); wptr 1710 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 1711 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 1713 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 1836 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 1837 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 1839 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 2051 drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c WARN_ON(ring->wptr % 2 || count % 2); wptr 669 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c ring->wptr = RREG32_SOC15(UVD, i, mmUVD_JRBC_RB_WPTR); wptr 864 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c ring->wptr = RREG32_SOC15(UVD, i, mmUVD_RBC_RB_RPTR); wptr 866 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c lower_32_bits(ring->wptr)); wptr 868 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); wptr 869 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); wptr 875 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); wptr 876 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 993 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 994 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 996 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 1084 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 1085 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 1087 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); wptr 1091 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 1092 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 1094 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); wptr 1172 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); wptr 1173 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); wptr 1175 drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c WREG32_SOC15(UVD, ring->me, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); wptr 376 drivers/gpu/drm/amd/amdgpu/vega10_ih.c u32 wptr, reg, tmp; wptr 378 drivers/gpu/drm/amd/amdgpu/vega10_ih.c wptr = le32_to_cpu(*ih->wptr_cpu); wptr 380 drivers/gpu/drm/amd/amdgpu/vega10_ih.c if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) wptr 394 drivers/gpu/drm/amd/amdgpu/vega10_ih.c wptr = RREG32_NO_KIQ(reg); wptr 395 drivers/gpu/drm/amd/amdgpu/vega10_ih.c if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW)) wptr 398 drivers/gpu/drm/amd/amdgpu/vega10_ih.c wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0); wptr 404 drivers/gpu/drm/amd/amdgpu/vega10_ih.c tmp = (wptr + 32) & ih->ptr_mask; wptr 407 drivers/gpu/drm/amd/amdgpu/vega10_ih.c wptr, ih->rptr, tmp); wptr 424 drivers/gpu/drm/amd/amdgpu/vega10_ih.c return (wptr & ih->ptr_mask); wptr 541 drivers/gpu/drm/amd/amdgpu/vega10_ih.c uint32_t wptr = cpu_to_le32(entry->src_data[0]); wptr 545 drivers/gpu/drm/amd/amdgpu/vega10_ih.c *adev->irq.ih1.wptr_cpu = wptr; wptr 549 drivers/gpu/drm/amd/amdgpu/vega10_ih.c *adev->irq.ih2.wptr_cpu = wptr; wptr 215 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c uint32_t wptr, rptr; wptr 225 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c wptr = kq->pending_wptr; wptr 231 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c pr_debug("wptr: %d\n", wptr); wptr 234 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c available_size = (rptr + queue_size_dwords - 1 - wptr) % wptr 245 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c if (wptr + packet_size_in_dwords >= queue_size_dwords) { wptr 253 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c while (wptr > 0) { wptr 254 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c queue_address[wptr] = kq->nop_packet; wptr 255 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c wptr = (wptr + 1) % queue_size_dwords; wptr 260 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c *buffer_ptr = &queue_address[wptr]; wptr 261 drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c kq->pending_wptr = wptr + packet_size_in_dwords; wptr 30 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c static inline void inc_wptr(unsigned int *wptr, unsigned int increment_bytes, wptr 33 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c unsigned int temp = *wptr + increment_bytes / sizeof(uint32_t); wptr 37 drivers/gpu/drm/amd/amdkfd/kfd_packet_manager.c *wptr = temp; wptr 255 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t queue_id, uint32_t __user *wptr, wptr 260 drivers/gpu/drm/amd/include/kgd_kfd_interface.h uint32_t __user *wptr, struct mm_struct *mm); wptr 25 drivers/gpu/drm/msm/adreno/a5xx_gpu.c uint32_t wptr; wptr 34 drivers/gpu/drm/msm/adreno/a5xx_gpu.c wptr = get_wptr(ring); wptr 43 drivers/gpu/drm/msm/adreno/a5xx_gpu.c gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); wptr 104 drivers/gpu/drm/msm/adreno/a5xx_gpu.h uint32_t wptr; wptr 43 drivers/gpu/drm/msm/adreno/a5xx_preempt.c uint32_t wptr; wptr 49 drivers/gpu/drm/msm/adreno/a5xx_preempt.c wptr = get_wptr(ring); wptr 52 drivers/gpu/drm/msm/adreno/a5xx_preempt.c gpu_write(gpu, REG_A5XX_CP_RB_WPTR, wptr); wptr 136 drivers/gpu/drm/msm/adreno/a5xx_preempt.c a5xx_gpu->preempt[ring->id]->wptr = get_wptr(ring); wptr 210 drivers/gpu/drm/msm/adreno/a5xx_preempt.c a5xx_gpu->preempt[i]->wptr = 0; wptr 54 drivers/gpu/drm/msm/adreno/a6xx_gpu.c uint32_t wptr; wptr 63 drivers/gpu/drm/msm/adreno/a6xx_gpu.c wptr = get_wptr(ring); wptr 70 drivers/gpu/drm/msm/adreno/a6xx_gpu.c gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr); wptr 489 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t wptr; wptr 499 drivers/gpu/drm/msm/adreno/adreno_gpu.c wptr = get_wptr(ring); wptr 504 drivers/gpu/drm/msm/adreno/adreno_gpu.c adreno_gpu_write(adreno_gpu, REG_ADRENO_CP_RB_WPTR, wptr); wptr 510 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t wptr = get_wptr(ring); wptr 513 drivers/gpu/drm/msm/adreno/adreno_gpu.c if (!spin_until(get_rptr(adreno_gpu, ring) == wptr)) wptr 518 drivers/gpu/drm/msm/adreno/adreno_gpu.c gpu->name, ring->id, get_rptr(adreno_gpu, ring), wptr); wptr 539 drivers/gpu/drm/msm/adreno/adreno_gpu.c state->ring[i].wptr = get_wptr(gpu->rb[i]); wptr 542 drivers/gpu/drm/msm/adreno/adreno_gpu.c size = state->ring[i].wptr; wptr 545 drivers/gpu/drm/msm/adreno/adreno_gpu.c for (j = state->ring[i].wptr; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) wptr 719 drivers/gpu/drm/msm/adreno/adreno_gpu.c drm_printf(p, " wptr: %d\n", state->ring[i].wptr); wptr 807 drivers/gpu/drm/msm/adreno/adreno_gpu.c uint32_t wptr = ring->next - ring->start; wptr 809 drivers/gpu/drm/msm/adreno/adreno_gpu.c return (rptr + (size - 1) - wptr) % size; wptr 196 drivers/gpu/drm/msm/msm_gpu.h u32 wptr; wptr 3748 drivers/gpu/drm/radeon/cik.c next_rptr = ring->wptr + 3 + 4; wptr 3754 drivers/gpu/drm/radeon/cik.c next_rptr = ring->wptr + 5 + 4; wptr 4092 drivers/gpu/drm/radeon/cik.c ring->wptr = 0; wptr 4093 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_WPTR, ring->wptr); wptr 4149 drivers/gpu/drm/radeon/cik.c WREG32(CP_RB0_WPTR, ring->wptr); wptr 4174 drivers/gpu/drm/radeon/cik.c u32 wptr; wptr 4178 drivers/gpu/drm/radeon/cik.c wptr = rdev->wb.wb[ring->wptr_offs/4]; wptr 4182 drivers/gpu/drm/radeon/cik.c wptr = RREG32(CP_HQD_PQ_WPTR); wptr 4187 drivers/gpu/drm/radeon/cik.c return wptr; wptr 4194 drivers/gpu/drm/radeon/cik.c rdev->wb.wb[ring->wptr_offs/4] = ring->wptr; wptr 4195 drivers/gpu/drm/radeon/cik.c WDOORBELL32(ring->doorbell_index, ring->wptr); wptr 4731 drivers/gpu/drm/radeon/cik.c rdev->ring[idx].wptr = 0; wptr 4732 drivers/gpu/drm/radeon/cik.c mqd->queue_state.cp_hqd_pq_wptr = rdev->ring[idx].wptr; wptr 7498 drivers/gpu/drm/radeon/cik.c u32 wptr, tmp; wptr 7501 drivers/gpu/drm/radeon/cik.c wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); wptr 7503 drivers/gpu/drm/radeon/cik.c wptr = RREG32(IH_RB_WPTR); wptr 7505 drivers/gpu/drm/radeon/cik.c if (wptr & RB_OVERFLOW) { wptr 7506 drivers/gpu/drm/radeon/cik.c wptr &= ~RB_OVERFLOW; wptr 7512 drivers/gpu/drm/radeon/cik.c wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); wptr 7513 drivers/gpu/drm/radeon/cik.c rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; wptr 7518 drivers/gpu/drm/radeon/cik.c return (wptr & rdev->ih.ptr_mask); wptr 7557 drivers/gpu/drm/radeon/cik.c u32 wptr; wptr 7571 drivers/gpu/drm/radeon/cik.c wptr = cik_get_ih_wptr(rdev); wptr 7579 drivers/gpu/drm/radeon/cik.c DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr); wptr 7587 drivers/gpu/drm/radeon/cik.c while (rptr != wptr) { wptr 8118 drivers/gpu/drm/radeon/cik.c wptr = cik_get_ih_wptr(rdev); wptr 8119 drivers/gpu/drm/radeon/cik.c if (wptr != rptr) wptr 121 drivers/gpu/drm/radeon/cik_sdma.c WREG32(reg, (ring->wptr << 2) & 0x3fffc); wptr 140 drivers/gpu/drm/radeon/cik_sdma.c u32 next_rptr = ring->wptr + 5; wptr 152 drivers/gpu/drm/radeon/cik_sdma.c while ((ring->wptr & 7) != 4) wptr 411 drivers/gpu/drm/radeon/cik_sdma.c ring->wptr = 0; wptr 412 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2); wptr 2940 drivers/gpu/drm/radeon/evergreen.c next_rptr = ring->wptr + 3 + 4; wptr 2946 drivers/gpu/drm/radeon/evergreen.c next_rptr = ring->wptr + 5 + 4; wptr 3098 drivers/gpu/drm/radeon/evergreen.c ring->wptr = 0; wptr 3099 drivers/gpu/drm/radeon/evergreen.c WREG32(CP_RB_WPTR, ring->wptr); wptr 4678 drivers/gpu/drm/radeon/evergreen.c u32 wptr, tmp; wptr 4681 drivers/gpu/drm/radeon/evergreen.c wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); wptr 4683 drivers/gpu/drm/radeon/evergreen.c wptr = RREG32(IH_RB_WPTR); wptr 4685 drivers/gpu/drm/radeon/evergreen.c if (wptr & RB_OVERFLOW) { wptr 4686 drivers/gpu/drm/radeon/evergreen.c wptr &= ~RB_OVERFLOW; wptr 4692 drivers/gpu/drm/radeon/evergreen.c wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); wptr 4693 drivers/gpu/drm/radeon/evergreen.c rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; wptr 4698 drivers/gpu/drm/radeon/evergreen.c return (wptr & rdev->ih.ptr_mask); wptr 4707 drivers/gpu/drm/radeon/evergreen.c u32 wptr; wptr 4721 drivers/gpu/drm/radeon/evergreen.c wptr = evergreen_get_ih_wptr(rdev); wptr 4729 drivers/gpu/drm/radeon/evergreen.c DRM_DEBUG("evergreen_irq_process start: rptr %d, wptr %d\n", rptr, wptr); wptr 4737 drivers/gpu/drm/radeon/evergreen.c while (rptr != wptr) { wptr 4925 drivers/gpu/drm/radeon/evergreen.c wptr = evergreen_get_ih_wptr(rdev); wptr 4926 drivers/gpu/drm/radeon/evergreen.c if (wptr != rptr) wptr 73 drivers/gpu/drm/radeon/evergreen_dma.c u32 next_rptr = ring->wptr + 4; wptr 86 drivers/gpu/drm/radeon/evergreen_dma.c while ((ring->wptr & 7) != 5) wptr 1437 drivers/gpu/drm/radeon/ni.c uint32_t next_rptr = ring->wptr + 3 + 4 + 8; wptr 1496 drivers/gpu/drm/radeon/ni.c u32 wptr; wptr 1499 drivers/gpu/drm/radeon/ni.c wptr = RREG32(CP_RB0_WPTR); wptr 1501 drivers/gpu/drm/radeon/ni.c wptr = RREG32(CP_RB1_WPTR); wptr 1503 drivers/gpu/drm/radeon/ni.c wptr = RREG32(CP_RB2_WPTR); wptr 1505 drivers/gpu/drm/radeon/ni.c return wptr; wptr 1512 drivers/gpu/drm/radeon/ni.c WREG32(CP_RB0_WPTR, ring->wptr); wptr 1515 drivers/gpu/drm/radeon/ni.c WREG32(CP_RB1_WPTR, ring->wptr); wptr 1518 drivers/gpu/drm/radeon/ni.c WREG32(CP_RB2_WPTR, ring->wptr); wptr 1718 drivers/gpu/drm/radeon/ni.c ring->wptr = 0; wptr 1720 drivers/gpu/drm/radeon/ni.c WREG32(cp_rb_wptr[i], ring->wptr); wptr 111 drivers/gpu/drm/radeon/ni_dma.c WREG32(reg, (ring->wptr << 2) & 0x3fffc); wptr 129 drivers/gpu/drm/radeon/ni_dma.c u32 next_rptr = ring->wptr + 4; wptr 142 drivers/gpu/drm/radeon/ni_dma.c while ((ring->wptr & 7) != 5) wptr 243 drivers/gpu/drm/radeon/ni_dma.c ring->wptr = 0; wptr 244 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); wptr 1084 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_WPTR, ring->wptr); wptr 1183 drivers/gpu/drm/radeon/r100.c ring->wptr = 0; wptr 1184 drivers/gpu/drm/radeon/r100.c WREG32(RADEON_CP_RB_WPTR, ring->wptr); wptr 3696 drivers/gpu/drm/radeon/r100.c u32 next_rptr = ring->wptr + 2 + 3; wptr 2639 drivers/gpu/drm/radeon/r600.c WREG32(R600_CP_RB_WPTR, ring->wptr); wptr 2743 drivers/gpu/drm/radeon/r600.c ring->wptr = 0; wptr 2744 drivers/gpu/drm/radeon/r600.c WREG32(CP_RB_WPTR, ring->wptr); wptr 3375 drivers/gpu/drm/radeon/r600.c next_rptr = ring->wptr + 3 + 4; wptr 3381 drivers/gpu/drm/radeon/r600.c next_rptr = ring->wptr + 5 + 4; wptr 4042 drivers/gpu/drm/radeon/r600.c u32 wptr, tmp; wptr 4045 drivers/gpu/drm/radeon/r600.c wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); wptr 4047 drivers/gpu/drm/radeon/r600.c wptr = RREG32(IH_RB_WPTR); wptr 4049 drivers/gpu/drm/radeon/r600.c if (wptr & RB_OVERFLOW) { wptr 4050 drivers/gpu/drm/radeon/r600.c wptr &= ~RB_OVERFLOW; wptr 4056 drivers/gpu/drm/radeon/r600.c wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); wptr 4057 drivers/gpu/drm/radeon/r600.c rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; wptr 4062 drivers/gpu/drm/radeon/r600.c return (wptr & rdev->ih.ptr_mask); wptr 4097 drivers/gpu/drm/radeon/r600.c u32 wptr; wptr 4112 drivers/gpu/drm/radeon/r600.c wptr = r600_get_ih_wptr(rdev); wptr 4120 drivers/gpu/drm/radeon/r600.c DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); wptr 4128 drivers/gpu/drm/radeon/r600.c while (rptr != wptr) { wptr 4337 drivers/gpu/drm/radeon/r600.c wptr = r600_get_ih_wptr(rdev); wptr 4338 drivers/gpu/drm/radeon/r600.c if (wptr != rptr) wptr 89 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_WPTR, (ring->wptr << 2) & 0x3fffc); wptr 167 drivers/gpu/drm/radeon/r600_dma.c ring->wptr = 0; wptr 168 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_WPTR, ring->wptr << 2); wptr 410 drivers/gpu/drm/radeon/r600_dma.c u32 next_rptr = ring->wptr + 4; wptr 423 drivers/gpu/drm/radeon/r600_dma.c while ((ring->wptr & 7) != 5) wptr 840 drivers/gpu/drm/radeon/radeon.h unsigned wptr; wptr 2690 drivers/gpu/drm/radeon/radeon.h ring->ring[ring->wptr++] = v; wptr 2691 drivers/gpu/drm/radeon/radeon.h ring->wptr &= ring->ptr_mask; wptr 88 drivers/gpu/drm/radeon/radeon_ring.c ring->ring_free_dw -= ring->wptr; wptr 129 drivers/gpu/drm/radeon/radeon_ring.c ring->wptr_old = ring->wptr; wptr 177 drivers/gpu/drm/radeon/radeon_ring.c while (ring->wptr & ring->align_mask) { wptr 215 drivers/gpu/drm/radeon/radeon_ring.c ring->wptr = ring->wptr_old; wptr 312 drivers/gpu/drm/radeon/radeon_ring.c size = ring->wptr + (ring->ring_size / 4); wptr 472 drivers/gpu/drm/radeon/radeon_ring.c uint32_t rptr, wptr, rptr_next; wptr 478 drivers/gpu/drm/radeon/radeon_ring.c wptr = radeon_ring_get_wptr(rdev, ring); wptr 480 drivers/gpu/drm/radeon/radeon_ring.c wptr, wptr); wptr 494 drivers/gpu/drm/radeon/radeon_ring.c ring->wptr, ring->wptr); wptr 3419 drivers/gpu/drm/radeon/si.c next_rptr = ring->wptr + 3 + 4 + 8; wptr 3425 drivers/gpu/drm/radeon/si.c next_rptr = ring->wptr + 5 + 4 + 8; wptr 3678 drivers/gpu/drm/radeon/si.c ring->wptr = 0; wptr 3679 drivers/gpu/drm/radeon/si.c WREG32(CP_RB0_WPTR, ring->wptr); wptr 3709 drivers/gpu/drm/radeon/si.c ring->wptr = 0; wptr 3710 drivers/gpu/drm/radeon/si.c WREG32(CP_RB1_WPTR, ring->wptr); wptr 3733 drivers/gpu/drm/radeon/si.c ring->wptr = 0; wptr 3734 drivers/gpu/drm/radeon/si.c WREG32(CP_RB2_WPTR, ring->wptr); wptr 6212 drivers/gpu/drm/radeon/si.c u32 wptr, tmp; wptr 6215 drivers/gpu/drm/radeon/si.c wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]); wptr 6217 drivers/gpu/drm/radeon/si.c wptr = RREG32(IH_RB_WPTR); wptr 6219 drivers/gpu/drm/radeon/si.c if (wptr & RB_OVERFLOW) { wptr 6220 drivers/gpu/drm/radeon/si.c wptr &= ~RB_OVERFLOW; wptr 6226 drivers/gpu/drm/radeon/si.c wptr, rdev->ih.rptr, (wptr + 16) & rdev->ih.ptr_mask); wptr 6227 drivers/gpu/drm/radeon/si.c rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask; wptr 6232 drivers/gpu/drm/radeon/si.c return (wptr & rdev->ih.ptr_mask); wptr 6250 drivers/gpu/drm/radeon/si.c u32 wptr; wptr 6263 drivers/gpu/drm/radeon/si.c wptr = si_get_ih_wptr(rdev); wptr 6271 drivers/gpu/drm/radeon/si.c DRM_DEBUG("si_irq_process start: rptr %d, wptr %d\n", rptr, wptr); wptr 6279 drivers/gpu/drm/radeon/si.c while (rptr != wptr) { wptr 6449 drivers/gpu/drm/radeon/si.c wptr = si_get_ih_wptr(rdev); wptr 6450 drivers/gpu/drm/radeon/si.c if (wptr != rptr) wptr 70 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_RBC_RB_WPTR, ring->wptr); wptr 370 drivers/gpu/drm/radeon/uvd_v1_0.c ring->wptr = RREG32(UVD_RBC_RB_RPTR); wptr 371 drivers/gpu/drm/radeon/uvd_v1_0.c WREG32(UVD_RBC_RB_WPTR, ring->wptr); wptr 97 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_WPTR, ring->wptr); wptr 99 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_WPTR2, ring->wptr); wptr 298 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_RPTR, ring->wptr); wptr 299 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_WPTR, ring->wptr); wptr 305 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_RPTR2, ring->wptr); wptr 306 drivers/gpu/drm/radeon/vce_v1_0.c WREG32(VCE_RB_WPTR2, ring->wptr); wptr 584 drivers/infiniband/hw/cxgb3/cxio_hal.c __func__, rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, len, wptr 588 drivers/infiniband/hw/cxgb3/cxio_hal.c if (Q_FULL(rdev_p->ctrl_qp.rptr, rdev_p->ctrl_qp.wptr, wptr 592 drivers/infiniband/hw/cxgb3/cxio_hal.c rdev_p->ctrl_qp.wptr, rdev_p->ctrl_qp.rptr, i); wptr 595 drivers/infiniband/hw/cxgb3/cxio_hal.c rdev_p->ctrl_qp.wptr, wptr 604 drivers/infiniband/hw/cxgb3/cxio_hal.c wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % wptr 646 drivers/infiniband/hw/cxgb3/cxio_hal.c wqe = (__be64 *)(rdev_p->ctrl_qp.workq + (rdev_p->ctrl_qp.wptr % wptr 650 drivers/infiniband/hw/cxgb3/cxio_hal.c ((union t3_wrid *)(wqe+1))->id0.low = rdev_p->ctrl_qp.wptr; wptr 657 drivers/infiniband/hw/cxgb3/cxio_hal.c Q_GENBIT(rdev_p->ctrl_qp.wptr, wptr 663 drivers/infiniband/hw/cxgb3/cxio_hal.c rdev_p->ctrl_qp.wptr++; wptr 681 drivers/infiniband/hw/cxgb3/cxio_hal.c u32 wptr; wptr 729 drivers/infiniband/hw/cxgb3/cxio_hal.c wptr = rdev_p->ctrl_qp.wptr; wptr 734 drivers/infiniband/hw/cxgb3/cxio_hal.c wptr))) wptr 742 drivers/infiniband/hw/cxgb3/cxio_hal.c u32 wptr; wptr 752 drivers/infiniband/hw/cxgb3/cxio_hal.c wptr = rdev_p->ctrl_qp.wptr; wptr 759 drivers/infiniband/hw/cxgb3/cxio_hal.c wptr))) wptr 1089 drivers/infiniband/hw/cxgb3/cxio_hal.c u32 wptr = Q_PTR2IDX(wq->sq_wptr, wq->sq_size_log2); wptr 1091 drivers/infiniband/hw/cxgb3/cxio_hal.c while (Q_PTR2IDX(rptr, wq->sq_size_log2) != wptr) { wptr 1305 drivers/infiniband/hw/cxgb3/cxio_hal.c if (((cq->rptr - cq->wptr) > (1 << (cq->size_log2 - 1))) wptr 1306 drivers/infiniband/hw/cxgb3/cxio_hal.c || ((cq->rptr - cq->wptr) >= 128)) { wptr 1307 drivers/infiniband/hw/cxgb3/cxio_hal.c *credit = cq->rptr - cq->wptr; wptr 1308 drivers/infiniband/hw/cxgb3/cxio_hal.c cq->wptr = cq->rptr; wptr 68 drivers/infiniband/hw/cxgb3/cxio_hal.h u32 wptr; wptr 46 drivers/infiniband/hw/cxgb3/cxio_wr.h #define Q_EMPTY(rptr,wptr) ((rptr)==(wptr)) wptr 47 drivers/infiniband/hw/cxgb3/cxio_wr.h #define Q_FULL(rptr,wptr,size_log2) ( (((wptr)-(rptr))>>(size_log2)) && \ wptr 48 drivers/infiniband/hw/cxgb3/cxio_wr.h ((rptr)!=(wptr)) ) wptr 50 drivers/infiniband/hw/cxgb3/cxio_wr.h #define Q_FREECNT(rptr,wptr,size_log2) ((1UL<<size_log2)-((wptr)-(rptr))) wptr 51 drivers/infiniband/hw/cxgb3/cxio_wr.h #define Q_COUNT(rptr,wptr) ((wptr)-(rptr)) wptr 697 drivers/infiniband/hw/cxgb3/cxio_wr.h u32 wptr; /* idx to next available WR slot */ wptr 718 drivers/infiniband/hw/cxgb3/cxio_wr.h u32 wptr; wptr 176 drivers/infiniband/hw/cxgb3/iwch_qp.c Q_PTR2IDX((wq->wptr+1), wq->size_log2)); wptr 178 drivers/infiniband/hw/cxgb3/iwch_qp.c Q_GENBIT(wq->wptr + 1, wq->size_log2), wptr 385 drivers/infiniband/hw/cxgb3/iwch_qp.c idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2); wptr 444 drivers/infiniband/hw/cxgb3/iwch_qp.c Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), wptr 453 drivers/infiniband/hw/cxgb3/iwch_qp.c qhp->wq.wptr += wr_cnt; wptr 495 drivers/infiniband/hw/cxgb3/iwch_qp.c idx = Q_PTR2IDX(qhp->wq.wptr, qhp->wq.size_log2); wptr 509 drivers/infiniband/hw/cxgb3/iwch_qp.c Q_GENBIT(qhp->wq.wptr, qhp->wq.size_log2), wptr 515 drivers/infiniband/hw/cxgb3/iwch_qp.c ++(qhp->wq.wptr); wptr 55 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c const char *wptr; wptr 60 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c wptr = NULL; wptr 68 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c wptr = buf; wptr 73 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c *wstrPtr = wptr; wptr 182 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c const char *wptr; wptr 186 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); wptr 189 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (!wptr) return 0; wptr 191 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c pvr2_trace(PVR2_TRACE_DEBUGIFC,"debugifc cmd: \"%.*s\"",wlen,wptr); wptr 192 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (debugifc_match_keyword(wptr,wlen,"reset")) { wptr 193 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); wptr 196 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (!wptr) return -EINVAL; wptr 197 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (debugifc_match_keyword(wptr,wlen,"cpu")) { wptr 201 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"bus")) { wptr 203 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"soft")) { wptr 205 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"deep")) { wptr 207 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"firmware")) { wptr 209 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"decoder")) { wptr 211 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"worker")) { wptr 213 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"usbstats")) { wptr 219 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"cpufw")) { wptr 220 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); wptr 223 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (!wptr) return -EINVAL; wptr 224 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (debugifc_match_keyword(wptr,wlen,"fetch")) { wptr 225 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); wptr 226 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (scnt && wptr) { wptr 228 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (debugifc_match_keyword(wptr, wlen, wptr 231 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr, wlen, wptr 234 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr, wlen, wptr 243 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"done")) { wptr 249 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (debugifc_match_keyword(wptr,wlen,"gpio")) { wptr 253 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); wptr 256 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (!wptr) return -EINVAL; wptr 257 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (debugifc_match_keyword(wptr,wlen,"dir")) { wptr 259 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c } else if (!debugifc_match_keyword(wptr,wlen,"out")) { wptr 262 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); wptr 265 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (!wptr) return -EINVAL; wptr 266 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c ret = debugifc_parse_unsigned_number(wptr,wlen,&msk); wptr 268 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c scnt = debugifc_isolate_word(buf,count,&wptr,&wlen); wptr 269 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c if (wptr) { wptr 270 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c ret = debugifc_parse_unsigned_number(wptr,wlen,&val); wptr 284 drivers/media/usb/pvrusb2/pvrusb2-debugifc.c "debugifc failed to recognize cmd: \"%.*s\"",wlen,wptr); wptr 777 drivers/net/ethernet/cortina/gemini.c w = rw.bits.wptr; wptr 889 drivers/net/ethernet/cortina/gemini.c pn = (refill ? rw.bits.wptr : rw.bits.rptr) >> fpp_order; wptr 1250 drivers/net/ethernet/cortina/gemini.c w = rw.bits.wptr; wptr 1420 drivers/net/ethernet/cortina/gemini.c w = rw.bits.wptr; wptr 192 drivers/net/ethernet/cortina/gemini.h unsigned int wptr : 16; /* Write Ptr, RW */ wptr 948 drivers/net/ethernet/cortina/gemini.h unsigned int wptr:16; wptr 240 drivers/net/ethernet/micrel/ks8851_mll.c static inline void ks_inblk(struct ks_net *ks, u16 *wptr, u32 len) wptr 244 drivers/net/ethernet/micrel/ks8851_mll.c *wptr++ = (u16)ioread16(ks->hw_addr); wptr 254 drivers/net/ethernet/micrel/ks8851_mll.c static inline void ks_outblk(struct ks_net *ks, u16 *wptr, u32 len) wptr 258 drivers/net/ethernet/micrel/ks8851_mll.c iowrite16(*wptr++, ks->hw_addr); wptr 4148 drivers/net/ethernet/sun/cassini.c u32 wptr, rptr; wptr 4160 drivers/net/ethernet/sun/cassini.c wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR); wptr 4162 drivers/net/ethernet/sun/cassini.c if ((val == 0) && (wptr != rptr)) { wptr 4165 drivers/net/ethernet/sun/cassini.c val, wptr, rptr); wptr 168 drivers/net/ethernet/tehuti/tehuti.c f->wptr = 0; wptr 1104 drivers/net/ethernet/tehuti/tehuti.c rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); wptr 1112 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr += sizeof(struct rxf_desc); wptr 1113 drivers/net/ethernet/tehuti/tehuti.c delta = f->m.wptr - f->m.memsz; wptr 1115 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr = delta; wptr 1124 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); wptr 1159 drivers/net/ethernet/tehuti/tehuti.c rxfd = (struct rxf_desc *)(f->m.va + f->m.wptr); wptr 1167 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr += sizeof(struct rxf_desc); wptr 1168 drivers/net/ethernet/tehuti/tehuti.c delta = f->m.wptr - f->m.memsz; wptr 1170 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr = delta; wptr 1211 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_WR_PTR; wptr 1213 drivers/net/ethernet/tehuti/tehuti.c size = f->m.wptr - f->m.rptr; wptr 1370 drivers/net/ethernet/tehuti/tehuti.c int taken = db->wptr - db->rptr; wptr 1387 drivers/net/ethernet/tehuti/tehuti.c *pptr != db->wptr); /* or write pointer */ wptr 1403 drivers/net/ethernet/tehuti/tehuti.c BDX_ASSERT(db->rptr == db->wptr); /* can't read from empty db */ wptr 1413 drivers/net/ethernet/tehuti/tehuti.c __bdx_tx_db_ptr_next(db, &db->wptr); wptr 1414 drivers/net/ethernet/tehuti/tehuti.c BDX_ASSERT(db->rptr == db->wptr); /* we can not get empty db as wptr 1443 drivers/net/ethernet/tehuti/tehuti.c d->wptr = d->start; wptr 1492 drivers/net/ethernet/tehuti/tehuti.c db->wptr->len = skb_headlen(skb); wptr 1493 drivers/net/ethernet/tehuti/tehuti.c db->wptr->addr.dma = pci_map_single(priv->pdev, skb->data, wptr 1494 drivers/net/ethernet/tehuti/tehuti.c db->wptr->len, PCI_DMA_TODEVICE); wptr 1495 drivers/net/ethernet/tehuti/tehuti.c pbl->len = CPU_CHIP_SWAP32(db->wptr->len); wptr 1496 drivers/net/ethernet/tehuti/tehuti.c pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); wptr 1497 drivers/net/ethernet/tehuti/tehuti.c pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); wptr 1507 drivers/net/ethernet/tehuti/tehuti.c db->wptr->len = skb_frag_size(frag); wptr 1508 drivers/net/ethernet/tehuti/tehuti.c db->wptr->addr.dma = skb_frag_dma_map(&priv->pdev->dev, frag, wptr 1513 drivers/net/ethernet/tehuti/tehuti.c pbl->len = CPU_CHIP_SWAP32(db->wptr->len); wptr 1514 drivers/net/ethernet/tehuti/tehuti.c pbl->pa_lo = CPU_CHIP_SWAP32(L32_64(db->wptr->addr.dma)); wptr 1515 drivers/net/ethernet/tehuti/tehuti.c pbl->pa_hi = CPU_CHIP_SWAP32(H32_64(db->wptr->addr.dma)); wptr 1520 drivers/net/ethernet/tehuti/tehuti.c db->wptr->len = -txd_sizes[nr_frags].bytes; wptr 1521 drivers/net/ethernet/tehuti/tehuti.c db->wptr->addr.skb = skb; wptr 1584 drivers/net/ethernet/tehuti/tehuti.c fsize = f->m.rptr - f->m.wptr; wptr 1621 drivers/net/ethernet/tehuti/tehuti.c BDX_ASSERT(f->m.wptr >= f->m.memsz); /* started with valid wptr */ wptr 1622 drivers/net/ethernet/tehuti/tehuti.c txdd = (struct txd_desc *)(f->m.va + f->m.wptr); wptr 1654 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr += txd_sizes[nr_frags].bytes; wptr 1655 drivers/net/ethernet/tehuti/tehuti.c len = f->m.wptr - f->m.memsz; wptr 1657 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr = len; wptr 1663 drivers/net/ethernet/tehuti/tehuti.c BDX_ASSERT(f->m.wptr >= f->m.memsz); /* finished with valid wptr */ wptr 1673 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); wptr 1678 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr & TXF_WPTR_WR_PTR); wptr 1686 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); wptr 1719 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr = READ_REG(priv, f->m.reg_WPTR) & TXF_WPTR_MASK; wptr 1722 drivers/net/ethernet/tehuti/tehuti.c while (f->m.wptr != f->m.rptr) { wptr 1743 drivers/net/ethernet/tehuti/tehuti.c BDX_ASSERT((f->m.wptr & TXF_WPTR_WR_PTR) >= f->m.memsz); wptr 1755 drivers/net/ethernet/tehuti/tehuti.c priv->txd_fifo0.m.wptr & TXF_WPTR_WR_PTR); wptr 1778 drivers/net/ethernet/tehuti/tehuti.c while (db->rptr != db->wptr) { wptr 1813 drivers/net/ethernet/tehuti/tehuti.c int i = f->m.memsz - f->m.wptr; wptr 1819 drivers/net/ethernet/tehuti/tehuti.c memcpy(f->m.va + f->m.wptr, data, size); wptr 1820 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr += size; wptr 1822 drivers/net/ethernet/tehuti/tehuti.c memcpy(f->m.va + f->m.wptr, data, i); wptr 1823 drivers/net/ethernet/tehuti/tehuti.c f->m.wptr = size - i; wptr 1824 drivers/net/ethernet/tehuti/tehuti.c memcpy(f->m.va, data + i, f->m.wptr); wptr 1826 drivers/net/ethernet/tehuti/tehuti.c WRITE_REG(priv, f->m.reg_WPTR, f->m.wptr & TXF_WPTR_WR_PTR); wptr 145 drivers/net/ethernet/tehuti/tehuti.h u32 rptr, wptr; /* cached values of RPTR and WPTR registers, wptr 201 drivers/net/ethernet/tehuti/tehuti.h struct tx_map *wptr; /* points to the next element to write */ wptr 580 drivers/net/ppp/bsd_comp.c unsigned char *wptr; wptr 586 drivers/net/ppp/bsd_comp.c if (wptr) \ wptr 588 drivers/net/ppp/bsd_comp.c *wptr++ = (unsigned char) (v); \ wptr 591 drivers/net/ppp/bsd_comp.c wptr = NULL; \ wptr 630 drivers/net/ppp/bsd_comp.c wptr = obuf; wptr 639 drivers/net/ppp/bsd_comp.c if (wptr) wptr 641 drivers/net/ppp/bsd_comp.c *wptr++ = PPP_ADDRESS(rptr); wptr 642 drivers/net/ppp/bsd_comp.c *wptr++ = PPP_CONTROL(rptr); wptr 643 drivers/net/ppp/bsd_comp.c *wptr++ = 0; wptr 644 drivers/net/ppp/bsd_comp.c *wptr++ = PPP_COMP; wptr 645 drivers/net/ppp/bsd_comp.c *wptr++ = db->seqno >> 8; wptr 646 drivers/net/ppp/bsd_comp.c *wptr++ = db->seqno; wptr 782 drivers/net/ppp/bsd_comp.c if (wptr == NULL) wptr 843 drivers/net/ppp/bsd_comp.c unsigned char *wptr; wptr 893 drivers/net/ppp/bsd_comp.c wptr = obuf; wptr 894 drivers/net/ppp/bsd_comp.c *wptr++ = adrs; wptr 895 drivers/net/ppp/bsd_comp.c *wptr++ = ctrl; wptr 896 drivers/net/ppp/bsd_comp.c *wptr++ = 0; wptr 994 drivers/net/ppp/bsd_comp.c wptr += codelen; wptr 995 drivers/net/ppp/bsd_comp.c p = wptr; wptr 1040 drivers/net/ppp/bsd_comp.c *wptr++ = finchar; wptr 190 drivers/net/ppp/ppp_deflate.c unsigned char *wptr; wptr 204 drivers/net/ppp/ppp_deflate.c wptr = obuf; wptr 209 drivers/net/ppp/ppp_deflate.c wptr[0] = PPP_ADDRESS(rptr); wptr 210 drivers/net/ppp/ppp_deflate.c wptr[1] = PPP_CONTROL(rptr); wptr 211 drivers/net/ppp/ppp_deflate.c put_unaligned_be16(PPP_COMP, wptr + 2); wptr 212 drivers/net/ppp/ppp_deflate.c wptr += PPP_HDRLEN; wptr 213 drivers/net/ppp/ppp_deflate.c put_unaligned_be16(state->seqno, wptr); wptr 214 drivers/net/ppp/ppp_deflate.c wptr += DEFLATE_OVHD; wptr 216 drivers/net/ppp/ppp_deflate.c state->strm.next_out = wptr; wptr 774 drivers/scsi/lpfc/lpfc_nvme.c uint32_t *wptr, *dptr; wptr 813 drivers/scsi/lpfc/lpfc_nvme.c wptr = &wqe->words[16]; /* WQE ptr */ wptr 817 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 1 */ wptr 818 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 2 */ wptr 819 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 3 */ wptr 820 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 4 */ wptr 822 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 6 */ wptr 823 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 7 */ wptr 825 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 16 */ wptr 826 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 17 */ wptr 827 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 18 */ wptr 828 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 19 */ wptr 829 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 20 */ wptr 830 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 21 */ wptr 831 drivers/scsi/lpfc/lpfc_nvme.c *wptr++ = *dptr++; /* Word 22 */ wptr 832 drivers/scsi/lpfc/lpfc_nvme.c *wptr = *dptr; /* Word 23 */ wptr 580 drivers/scsi/qla1280.c uint16_t *wptr; wptr 592 drivers/scsi/qla1280.c wptr = (uint16_t *)&ha->nvram; wptr 596 drivers/scsi/qla1280.c *wptr = qla1280_get_nvram_word(ha, cnt); wptr 597 drivers/scsi/qla1280.c chksum += *wptr & 0xff; wptr 598 drivers/scsi/qla1280.c chksum += (*wptr >> 8) & 0xff; wptr 599 drivers/scsi/qla1280.c wptr++; wptr 608 drivers/scsi/qla1280.c *wptr = qla1280_get_nvram_word(ha, cnt); wptr 609 drivers/scsi/qla1280.c chksum += *wptr & 0xff; wptr 610 drivers/scsi/qla1280.c chksum += (*wptr >> 8) & 0xff; wptr 611 drivers/scsi/qla1280.c wptr++; wptr 3345 drivers/scsi/qla1280.c uint16_t *wptr; wptr 3366 drivers/scsi/qla1280.c wptr = &mailbox[0]; wptr 3367 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox0); wptr 3368 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox1); wptr 3369 drivers/scsi/qla1280.c *wptr = RD_REG_WORD(®->mailbox2); wptr 3371 drivers/scsi/qla1280.c wptr++; wptr 3372 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox3); wptr 3373 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox4); wptr 3374 drivers/scsi/qla1280.c wptr++; wptr 3375 drivers/scsi/qla1280.c *wptr++ = RD_REG_WORD(®->mailbox6); wptr 3376 drivers/scsi/qla1280.c *wptr = RD_REG_WORD(®->mailbox7); wptr 3475 drivers/scsi/qla1280.c wptr = &mailbox[0]; wptr 3476 drivers/scsi/qla1280.c memcpy((uint16_t *) ha->mailbox_out, wptr, wptr 278 drivers/scsi/qla2xxx/qla_isr.c uint16_t __iomem *wptr; wptr 294 drivers/scsi/qla2xxx/qla_isr.c wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 1); wptr 298 drivers/scsi/qla2xxx/qla_isr.c wptr = (uint16_t __iomem *)MAILBOX_REG(ha, reg, 8); wptr 300 drivers/scsi/qla2xxx/qla_isr.c ha->mailbox_out[cnt] = qla2x00_debounce_register(wptr); wptr 302 drivers/scsi/qla2xxx/qla_isr.c ha->mailbox_out[cnt] = RD_REG_WORD(wptr); wptr 304 drivers/scsi/qla2xxx/qla_isr.c wptr++; wptr 317 drivers/scsi/qla2xxx/qla_isr.c uint16_t __iomem *wptr; wptr 322 drivers/scsi/qla2xxx/qla_isr.c wptr = (uint16_t __iomem *)®24->mailbox1; wptr 324 drivers/scsi/qla2xxx/qla_isr.c wptr = (uint16_t __iomem *)®82->mailbox_out[1]; wptr 328 drivers/scsi/qla2xxx/qla_isr.c for (cnt = 0; cnt < QLA_IDC_ACK_REGS; cnt++, wptr++) wptr 329 drivers/scsi/qla2xxx/qla_isr.c mb[cnt] = RD_REG_WORD(wptr); wptr 2926 drivers/scsi/qla2xxx/qla_isr.c uint16_t __iomem *wptr; wptr 2942 drivers/scsi/qla2xxx/qla_isr.c wptr = (uint16_t __iomem *)®->mailbox1; wptr 2946 drivers/scsi/qla2xxx/qla_isr.c ha->mailbox_out[cnt] = RD_REG_WORD(wptr); wptr 2949 drivers/scsi/qla2xxx/qla_isr.c wptr++; wptr 2876 drivers/scsi/qla2xxx/qla_mr.c uint32_t __iomem *wptr; wptr 2886 drivers/scsi/qla2xxx/qla_mr.c wptr = (uint32_t __iomem *)®->mailbox17; wptr 2889 drivers/scsi/qla2xxx/qla_mr.c ha->mailbox_out32[cnt] = RD_REG_DWORD(wptr); wptr 2890 drivers/scsi/qla2xxx/qla_mr.c wptr++; wptr 1999 drivers/scsi/qla2xxx/qla_nx.c uint16_t __iomem *wptr; wptr 2003 drivers/scsi/qla2xxx/qla_nx.c wptr = (uint16_t __iomem *)®->mailbox_out[1]; wptr 2010 drivers/scsi/qla2xxx/qla_nx.c ha->mailbox_out[cnt] = RD_REG_WORD(wptr); wptr 2011 drivers/scsi/qla2xxx/qla_nx.c wptr++; wptr 552 drivers/scsi/qla2xxx/qla_sup.c uint16_t cnt, chksum, *wptr; wptr 613 drivers/scsi/qla2xxx/qla_sup.c wptr = (void *)req->ring; wptr 614 drivers/scsi/qla2xxx/qla_sup.c cnt = sizeof(*fltl) / sizeof(*wptr); wptr 615 drivers/scsi/qla2xxx/qla_sup.c for (chksum = 0; cnt--; wptr++) wptr 616 drivers/scsi/qla2xxx/qla_sup.c chksum += le16_to_cpu(*wptr); wptr 674 drivers/scsi/qla2xxx/qla_sup.c uint16_t *wptr, cnt, chksum; wptr 684 drivers/scsi/qla2xxx/qla_sup.c wptr = (uint16_t *)ha->flt; wptr 688 drivers/scsi/qla2xxx/qla_sup.c if (le16_to_cpu(*wptr) == 0xffff) wptr 698 drivers/scsi/qla2xxx/qla_sup.c cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr); wptr 699 drivers/scsi/qla2xxx/qla_sup.c for (chksum = 0; cnt--; wptr++) wptr 700 drivers/scsi/qla2xxx/qla_sup.c chksum += le16_to_cpu(*wptr); wptr 952 drivers/scsi/qla2xxx/qla_sup.c uint16_t *wptr = (void *)req->ring; wptr 959 drivers/scsi/qla2xxx/qla_sup.c if (le16_to_cpu(*wptr) == 0xffff) wptr 964 drivers/scsi/qla2xxx/qla_sup.c for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++) wptr 965 drivers/scsi/qla2xxx/qla_sup.c chksum += le16_to_cpu(*wptr); wptr 1045 drivers/scsi/qla2xxx/qla_sup.c uint32_t *wptr; wptr 1052 drivers/scsi/qla2xxx/qla_sup.c wptr = (uint32_t *)req->ring; wptr 1055 drivers/scsi/qla2xxx/qla_sup.c if (*wptr == cpu_to_le32(0xffffffff)) { wptr 1059 drivers/scsi/qla2xxx/qla_sup.c ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr); wptr 1060 drivers/scsi/qla2xxx/qla_sup.c wptr++; wptr 1061 drivers/scsi/qla2xxx/qla_sup.c ha->fcoe_reset_timeout = le32_to_cpu(*wptr); wptr 1098 drivers/scsi/qla2xxx/qla_sup.c uint16_t *wptr; wptr 1139 drivers/scsi/qla2xxx/qla_sup.c for (wptr = data, chksum = 0; cnt--; wptr++) wptr 1140 drivers/scsi/qla2xxx/qla_sup.c chksum += le16_to_cpu(*wptr); wptr 1382 drivers/scsi/qla2xxx/qla_sup.c uint16_t *wptr; wptr 1386 drivers/scsi/qla2xxx/qla_sup.c wptr = (uint16_t *)buf; wptr 1389 drivers/scsi/qla2xxx/qla_sup.c wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, wptr 1425 drivers/scsi/qla2xxx/qla_sup.c uint16_t *wptr; wptr 1437 drivers/scsi/qla2xxx/qla_sup.c wptr = (uint16_t *)buf; wptr 1440 drivers/scsi/qla2xxx/qla_sup.c cpu_to_le16(*wptr)); wptr 1441 drivers/scsi/qla2xxx/qla_sup.c wptr++; wptr 3723 drivers/scsi/qla4xxx/ql4_nx.c uint16_t *wptr; wptr 3731 drivers/scsi/qla4xxx/ql4_nx.c wptr = (uint16_t *)ha->request_ring; wptr 3746 drivers/scsi/qla4xxx/ql4_nx.c if (*wptr == __constant_cpu_to_le16(0xffff)) wptr 3758 drivers/scsi/qla4xxx/ql4_nx.c chksum += le16_to_cpu(*wptr++); wptr 3837 drivers/scsi/qla4xxx/ql4_nx.c uint16_t *wptr; wptr 3846 drivers/scsi/qla4xxx/ql4_nx.c wptr = (uint16_t *)ha->request_ring; wptr 3851 drivers/scsi/qla4xxx/ql4_nx.c if (*wptr == __constant_cpu_to_le16(0xffff)) wptr 3860 drivers/scsi/qla4xxx/ql4_nx.c chksum += le16_to_cpu(*wptr++); wptr 3900 drivers/scsi/qla4xxx/ql4_nx.c uint32_t *wptr; wptr 3904 drivers/scsi/qla4xxx/ql4_nx.c wptr = (uint32_t *)ha->request_ring; wptr 3908 drivers/scsi/qla4xxx/ql4_nx.c if (*wptr == __constant_cpu_to_le32(0xffffffff)) { wptr 3912 drivers/scsi/qla4xxx/ql4_nx.c ha->nx_dev_init_timeout = le32_to_cpu(*wptr++); wptr 3913 drivers/scsi/qla4xxx/ql4_nx.c ha->nx_reset_timeout = le32_to_cpu(*wptr); wptr 270 drivers/tty/moxa.c u16 rptr, wptr, mask, len; wptr 274 drivers/tty/moxa.c wptr = readw(ofsAddr + RXwptr); wptr 276 drivers/tty/moxa.c len = (wptr - rptr) & mask; wptr 1989 drivers/tty/moxa.c u16 rptr, wptr, mask; wptr 1992 drivers/tty/moxa.c wptr = readw(ofsAddr + TXwptr); wptr 1994 drivers/tty/moxa.c return (wptr - rptr) & mask; wptr 2000 drivers/tty/moxa.c u16 rptr, wptr, mask; wptr 2003 drivers/tty/moxa.c wptr = readw(ofsAddr + TXwptr); wptr 2005 drivers/tty/moxa.c return mask - ((wptr - rptr) & mask); wptr 2011 drivers/tty/moxa.c u16 rptr, wptr, mask; wptr 2014 drivers/tty/moxa.c wptr = readw(ofsAddr + RXwptr); wptr 2016 drivers/tty/moxa.c return (wptr - rptr) & mask; wptr 298 drivers/tty/serial/men_z135_uart.c u32 wptr; wptr 320 drivers/tty/serial/men_z135_uart.c wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); wptr 321 drivers/tty/serial/men_z135_uart.c txc = (wptr >> 16) & 0x3ff; wptr 322 drivers/tty/serial/men_z135_uart.c wptr &= 0x3ff; wptr 338 drivers/tty/serial/men_z135_uart.c if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr)) wptr 339 drivers/tty/serial/men_z135_uart.c n = 4 - BYTES_TO_ALIGN(wptr); wptr 459 drivers/tty/serial/men_z135_uart.c u32 wptr; wptr 462 drivers/tty/serial/men_z135_uart.c wptr = ioread32(port->membase + MEN_Z135_TX_CTRL); wptr 463 drivers/tty/serial/men_z135_uart.c txc = (wptr >> 16) & 0x3ff; wptr 67 drivers/video/fbdev/maxinefb.c unsigned char *wptr; wptr 69 drivers/video/fbdev/maxinefb.c wptr = regs + 0xa0000 + (regno << 4); wptr 71 drivers/video/fbdev/maxinefb.c *((volatile unsigned short *) (wptr)) = val; wptr 98 drivers/watchdog/i6300esb.c #define to_esb_dev(wptr) container_of(wptr, struct esb_dev, wdd)