wpr_addr           50 drivers/gpu/drm/nouveau/include/nvkm/subdev/secboot.h 	u64 wpr_addr;
wpr_addr           49 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c 	u64 wpr_addr;
wpr_addr          352 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c 	cmd.wpr_lo = lower_32_bits(queue->wpr_addr);
wpr_addr          353 drivers/gpu/drm/nouveau/nvkm/falcon/msgqueue_0137c63d.c 	cmd.wpr_hi = upper_32_bits(queue->wpr_addr);
wpr_addr           77 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 			       const struct ls_ucode_img *img, u64 wpr_addr,
wpr_addr           84 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
wpr_addr          416 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 		      struct nvkm_gpuobj *wpr_blob, u64 wpr_addr)
wpr_addr          449 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 		ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc);
wpr_addr          487 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	u64 wpr_addr = sb->wpr_addr;
wpr_addr          561 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 		wpr_addr = acr->ls_blob->addr;
wpr_addr          563 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 			wpr_addr += acr->ls_blob->size / 2;
wpr_addr          579 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	ret = acr->func->ls_write_wpr(acr, &imgs, acr->ls_blob, wpr_addr);
wpr_addr          892 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 		wpr_range_lo = sb->wpr_addr;
wpr_addr         1139 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 			      const struct ls_ucode_img *img, u64 wpr_addr,
wpr_addr         1150 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r352.c 	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
wpr_addr           32 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 			       const struct ls_ucode_img *img, u64 wpr_addr,
wpr_addr           39 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
wpr_addr          117 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 			      const struct ls_ucode_img *img, u64 wpr_addr,
wpr_addr          126 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
wpr_addr          162 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 			       const struct ls_ucode_img *img, u64 wpr_addr,
wpr_addr          171 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r361.c 	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
wpr_addr          269 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c 		      struct nvkm_gpuobj *wpr_blob, u64 wpr_addr)
wpr_addr          301 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r367.c 		ls_func->generate_bl_desc(&acr->base, _img, wpr_addr, gdesc);
wpr_addr           32 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 			       const struct ls_ucode_img *img, u64 wpr_addr,
wpr_addr           39 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
wpr_addr           86 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 			       const struct ls_ucode_img *img, u64 wpr_addr,
wpr_addr           95 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r370.c 	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
wpr_addr           31 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c 			      const struct ls_ucode_img *img, u64 wpr_addr,
wpr_addr           40 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/acr_r375.c 	base = wpr_addr + img->ucode_off + pdesc->app_start_offset;
wpr_addr           53 drivers/gpu/drm/nouveau/nvkm/subdev/secboot/gm20b.c 	sb->wpr_addr = ioread32_native(mc + MC_SECURITY_CARVEOUT2_BOM_0) |