CNTR              292 drivers/dma/txx9dmac.c 			channel64_readl(dc, CNTR),
CNTR              304 drivers/dma/txx9dmac.c 			channel32_readl(dc, CNTR),
CNTR              323 drivers/dma/txx9dmac.c 	channel_writel(dc, CNTR, 0);
CNTR              348 drivers/dma/txx9dmac.c 		channel64_writel(dc, CNTR, 0);
CNTR              369 drivers/dma/txx9dmac.c 		channel32_writel(dc, CNTR, 0);
CNTR              474 drivers/dma/txx9dmac.c 			 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR);
CNTR              479 drivers/dma/txx9dmac.c 			 (u64)desc->CHAR, desc->SAR, desc->DAR, desc->CNTR,
CNTR              487 drivers/dma/txx9dmac.c 			 d->CHAR, d->SAR, d->DAR, d->CNTR);
CNTR              492 drivers/dma/txx9dmac.c 			 d->CHAR, d->SAR, d->DAR, d->CNTR,
CNTR              757 drivers/dma/txx9dmac.c 			desc->hwdesc.CNTR = xfer_count;
CNTR              763 drivers/dma/txx9dmac.c 			desc->hwdesc32.CNTR = xfer_count;
CNTR              848 drivers/dma/txx9dmac.c 			desc->hwdesc.CNTR = sg_dma_len(sg);
CNTR              857 drivers/dma/txx9dmac.c 			desc->hwdesc32.CNTR = sg_dma_len(sg);
CNTR               74 drivers/dma/txx9dmac.h 	TXX9_DMA_REG32(CNTR);	/* Count Register */
CNTR               84 drivers/dma/txx9dmac.h 	u32 CNTR;
CNTR              208 drivers/dma/txx9dmac.h 	TXX9_DMA_REG32(CNTR);
CNTR              214 drivers/dma/txx9dmac.h 	u32 CNTR;
CNTR             1388 drivers/infiniband/hw/hfi1/chip.c 	hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, ret, mode);
CNTR             1491 drivers/infiniband/hw/hfi1/chip.c 	hfi1_cdbg(CNTR, "csr 0x%x val 0x%llx mode %d", csr, data, mode);
CNTR             1541 drivers/infiniband/hw/hfi1/chip.c 	hfi1_cdbg(CNTR, "val 0x%llx mode %d", ret, mode);
CNTR             12089 drivers/infiniband/hw/hfi1/chip.c 			hfi1_cdbg(CNTR, "reading %s", entry->name);
CNTR             12092 drivers/infiniband/hw/hfi1/chip.c 				hfi1_cdbg(CNTR, "\tDisabled\n");
CNTR             12095 drivers/infiniband/hw/hfi1/chip.c 					hfi1_cdbg(CNTR, "\tPer VL\n");
CNTR             12102 drivers/infiniband/hw/hfi1/chip.c 						   CNTR,
CNTR             12109 drivers/infiniband/hw/hfi1/chip.c 					hfi1_cdbg(CNTR,
CNTR             12116 drivers/infiniband/hw/hfi1/chip.c 						hfi1_cdbg(CNTR,
CNTR             12127 drivers/infiniband/hw/hfi1/chip.c 					hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
CNTR             12155 drivers/infiniband/hw/hfi1/chip.c 			hfi1_cdbg(CNTR, "reading %s", entry->name);
CNTR             12158 drivers/infiniband/hw/hfi1/chip.c 				hfi1_cdbg(CNTR, "\tDisabled\n");
CNTR             12163 drivers/infiniband/hw/hfi1/chip.c 				hfi1_cdbg(CNTR, "\tPer VL");
CNTR             12169 drivers/infiniband/hw/hfi1/chip.c 					   CNTR,
CNTR             12180 drivers/infiniband/hw/hfi1/chip.c 				hfi1_cdbg(CNTR, "\tRead 0x%llx", val);
CNTR             12232 drivers/infiniband/hw/hfi1/chip.c 	hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
CNTR             12267 drivers/infiniband/hw/hfi1/chip.c 	hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
CNTR             12283 drivers/infiniband/hw/hfi1/chip.c 	hfi1_cdbg(CNTR, "cntr: %s vl %d psval 0x%llx", entry->name, vl, *psval);
CNTR             12301 drivers/infiniband/hw/hfi1/chip.c 	hfi1_cdbg(CNTR, "\tNew val=0x%llx", val);
CNTR             12399 drivers/infiniband/hw/hfi1/chip.c 	    CNTR,
CNTR             12409 drivers/infiniband/hw/hfi1/chip.c 		hfi1_cdbg(CNTR, "[%d] Tripwire counter rolled, updating",
CNTR             12413 drivers/infiniband/hw/hfi1/chip.c 		hfi1_cdbg(CNTR,
CNTR             12417 drivers/infiniband/hw/hfi1/chip.c 			hfi1_cdbg(CNTR, "[%d] 32bit limit hit, updating",
CNTR             12424 drivers/infiniband/hw/hfi1/chip.c 		hfi1_cdbg(CNTR, "[%d] Updating dd and ppd counters", dd->unit);
CNTR             12461 drivers/infiniband/hw/hfi1/chip.c 		hfi1_cdbg(CNTR, "[%d] setting last tx/rx to 0x%llx 0x%llx",
CNTR             12465 drivers/infiniband/hw/hfi1/chip.c 		hfi1_cdbg(CNTR, "[%d] No update necessary", dd->unit);
CNTR              522 drivers/infiniband/hw/hfi1/trace.c __hfi1_trace_fn(CNTR);
CNTR              123 drivers/infiniband/hw/hfi1/trace_dbg.h __hfi1_trace_def(CNTR);
CNTR               89 drivers/scsi/a2091.c 	regs->CNTR = cntr;
CNTR              122 drivers/scsi/a2091.c 	regs->CNTR = cntr;
CNTR              138 drivers/scsi/a2091.c 	regs->CNTR = CNTR_PDMD | CNTR_INTEN;
CNTR              206 drivers/scsi/a2091.c 	regs->CNTR = CNTR_PDMD | CNTR_INTEN;
CNTR              231 drivers/scsi/a2091.c 	hdata->regs->CNTR = 0;
CNTR               32 drivers/scsi/a2091.h 	volatile unsigned short	CNTR;
CNTR               88 drivers/scsi/a3000.c 	regs->CNTR = cntr;
CNTR              123 drivers/scsi/a3000.c 	regs->CNTR = cntr;
CNTR              146 drivers/scsi/a3000.c 	regs->CNTR = CNTR_PDMD | CNTR_INTEN;
CNTR              224 drivers/scsi/a3000.c 	regs->CNTR = CNTR_PDMD | CNTR_INTEN;
CNTR              250 drivers/scsi/a3000.c 	hdata->regs->CNTR = 0;
CNTR               34 drivers/scsi/a3000.h 	volatile unsigned short	CNTR;
CNTR               32 drivers/scsi/gvp11.c 	unsigned int status = hdata->regs->CNTR;
CNTR              123 drivers/scsi/gvp11.c 	regs->CNTR = cntr;
CNTR              157 drivers/scsi/gvp11.c 	regs->CNTR = GVP11_DMAC_INT_ENABLE;
CNTR              315 drivers/scsi/gvp11.c 	while (regs->CNTR & GVP11_DMAC_BUSY)
CNTR              317 drivers/scsi/gvp11.c 	regs->CNTR = 0;
CNTR              347 drivers/scsi/gvp11.c 	regs->CNTR = GVP11_DMAC_INT_ENABLE;
CNTR              371 drivers/scsi/gvp11.c 	hdata->regs->CNTR = 0;
CNTR               31 drivers/scsi/gvp11.h 	volatile unsigned short	CNTR;