wm_state 1308 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_state *wm_state, int level) wm_state 1314 drivers/gpu/drm/i915/intel_pm.c wm_state->wm.plane[plane_id] = USHRT_MAX; wm_state 1318 drivers/gpu/drm/i915/intel_pm.c wm_state->cxsr = false; wm_state 1319 drivers/gpu/drm/i915/intel_pm.c wm_state->sr.cursor = USHRT_MAX; wm_state 1320 drivers/gpu/drm/i915/intel_pm.c wm_state->sr.plane = USHRT_MAX; wm_state 1321 drivers/gpu/drm/i915/intel_pm.c wm_state->sr.fbc = USHRT_MAX; wm_state 1325 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll_en = false; wm_state 1326 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll.cursor = USHRT_MAX; wm_state 1327 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll.plane = USHRT_MAX; wm_state 1328 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll.fbc = USHRT_MAX; wm_state 1337 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; wm_state 1368 drivers/gpu/drm/i915/intel_pm.c wm_state->wm.plane[plane_id] = raw->plane[plane_id]; wm_state 1376 drivers/gpu/drm/i915/intel_pm.c wm_state->sr.plane = raw->plane[PLANE_PRIMARY]; wm_state 1377 drivers/gpu/drm/i915/intel_pm.c wm_state->sr.cursor = raw->plane[PLANE_CURSOR]; wm_state 1378 drivers/gpu/drm/i915/intel_pm.c wm_state->sr.fbc = raw->fbc; wm_state 1380 drivers/gpu/drm/i915/intel_pm.c wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY); wm_state 1388 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll.plane = raw->plane[PLANE_PRIMARY]; wm_state 1389 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll.cursor = raw->plane[PLANE_CURSOR]; wm_state 1390 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll.fbc = raw->fbc; wm_state 1392 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll_en = wm_state->cxsr; wm_state 1401 drivers/gpu/drm/i915/intel_pm.c g4x_invalidate_wms(crtc, wm_state, level); wm_state 1409 drivers/gpu/drm/i915/intel_pm.c wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL; wm_state 1412 drivers/gpu/drm/i915/intel_pm.c wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR)) wm_state 1413 drivers/gpu/drm/i915/intel_pm.c wm_state->fbc_en = false; wm_state 1415 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL)) wm_state 1416 drivers/gpu/drm/i915/intel_pm.c wm_state->fbc_en = false; wm_state 1508 drivers/gpu/drm/i915/intel_pm.c const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; wm_state 1513 drivers/gpu/drm/i915/intel_pm.c if (!wm_state->cxsr) wm_state 1515 drivers/gpu/drm/i915/intel_pm.c if (!wm_state->hpll_en) wm_state 1517 drivers/gpu/drm/i915/intel_pm.c if (!wm_state->fbc_en) wm_state 1530 drivers/gpu/drm/i915/intel_pm.c const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; wm_state 1533 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe] = wm_state->wm; wm_state 1535 drivers/gpu/drm/i915/intel_pm.c wm->sr = wm_state->sr; wm_state 1537 drivers/gpu/drm/i915/intel_pm.c wm->hpll = wm_state->hpll; wm_state 1747 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_state *wm_state, int level) wm_state 1755 drivers/gpu/drm/i915/intel_pm.c wm_state->wm[level].plane[plane_id] = USHRT_MAX; wm_state 1757 drivers/gpu/drm/i915/intel_pm.c wm_state->sr[level].cursor = USHRT_MAX; wm_state 1758 drivers/gpu/drm/i915/intel_pm.c wm_state->sr[level].plane = USHRT_MAX; wm_state 1856 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; wm_state 1910 drivers/gpu/drm/i915/intel_pm.c wm_state->num_levels = intel_wm_num_levels(dev_priv); wm_state 1916 drivers/gpu/drm/i915/intel_pm.c wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; wm_state 1918 drivers/gpu/drm/i915/intel_pm.c for (level = 0; level < wm_state->num_levels; level++) { wm_state 1926 drivers/gpu/drm/i915/intel_pm.c wm_state->wm[level].plane[plane_id] = wm_state 1931 drivers/gpu/drm/i915/intel_pm.c wm_state->sr[level].plane = wm_state 1937 drivers/gpu/drm/i915/intel_pm.c wm_state->sr[level].cursor = wm_state 1946 drivers/gpu/drm/i915/intel_pm.c wm_state->num_levels = level; wm_state 1949 drivers/gpu/drm/i915/intel_pm.c vlv_invalidate_wms(crtc, wm_state, level); wm_state 2115 drivers/gpu/drm/i915/intel_pm.c const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; wm_state 2120 drivers/gpu/drm/i915/intel_pm.c if (!wm_state->cxsr) wm_state 2124 drivers/gpu/drm/i915/intel_pm.c wm->level = min_t(int, wm->level, wm_state->num_levels - 1); wm_state 2134 drivers/gpu/drm/i915/intel_pm.c const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; wm_state 2137 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe] = wm_state->wm[wm->level]; wm_state 2139 drivers/gpu/drm/i915/intel_pm.c wm->sr = wm_state->sr[wm->level]; wm_state 6084 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; wm_state 6096 drivers/gpu/drm/i915/intel_pm.c wm_state->wm.plane[plane_id] = 0; wm_state 6106 drivers/gpu/drm/i915/intel_pm.c wm_state->sr.fbc = 0; wm_state 6107 drivers/gpu/drm/i915/intel_pm.c wm_state->hpll.fbc = 0; wm_state 6108 drivers/gpu/drm/i915/intel_pm.c wm_state->fbc_en = false; wm_state 6237 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; wm_state 6246 drivers/gpu/drm/i915/intel_pm.c for (level = 0; level < wm_state->num_levels; level++) { wm_state 6252 drivers/gpu/drm/i915/intel_pm.c wm_state->wm[level].plane[plane_id] =