wm 734 arch/mips/alchemy/devboards/db1300.c static void db1300_wm97xx_irqen(struct wm97xx *wm, int enable) wm 749 arch/mips/alchemy/devboards/db1300.c struct wm97xx *wm = platform_get_drvdata(pdev); wm 752 arch/mips/alchemy/devboards/db1300.c wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN, wm 757 arch/mips/alchemy/devboards/db1300.c wm97xx_config_gpio(wm, WM97XX_GPIO_3, WM97XX_GPIO_OUT, wm 761 arch/mips/alchemy/devboards/db1300.c wm->pen_irq = DB1300_AC97_PEN_INT; wm 763 arch/mips/alchemy/devboards/db1300.c return wm97xx_register_mach_ops(wm, &db1300_wm97xx_ops); wm 298 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h uint64_t wm:5; wm 300 arch/mips/include/asm/octeon/cvmx-uctlx-defs.h uint64_t wm:5; wm 59 arch/xtensa/kernel/signal.c unsigned long wm; wm 70 arch/xtensa/kernel/signal.c wm = (ws >> wb) | (ws << (XCHAL_NUM_AREGS / 4 - wb)); wm 83 arch/xtensa/kernel/signal.c int m = (wm >> base); wm 714 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static u32 dce_v10_0_dram_bandwidth(struct dce10_wm_params *wm) wm 722 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c yclk.full = dfixed_const(wm->yclk); wm 724 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 743 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static u32 dce_v10_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) wm 751 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c yclk.full = dfixed_const(wm->yclk); wm 753 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 772 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static u32 dce_v10_0_data_return_bandwidth(struct dce10_wm_params *wm) wm 780 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c sclk.full = dfixed_const(wm->sclk); wm 801 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static u32 dce_v10_0_dmif_request_bandwidth(struct dce10_wm_params *wm) wm 809 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c disp_clk.full = dfixed_const(wm->disp_clk); wm 832 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static u32 dce_v10_0_available_bandwidth(struct dce10_wm_params *wm) wm 835 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 dram_bandwidth = dce_v10_0_dram_bandwidth(wm); wm 836 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 data_return_bandwidth = dce_v10_0_data_return_bandwidth(wm); wm 837 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 dmif_req_bandwidth = dce_v10_0_dmif_request_bandwidth(wm); wm 851 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static u32 dce_v10_0_average_bandwidth(struct dce10_wm_params *wm) wm 864 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c line_time.full = dfixed_const(wm->active_time + wm->blank_time); wm 866 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c bpp.full = dfixed_const(wm->bytes_per_pixel); wm 867 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c src_width.full = dfixed_const(wm->src_width); wm 869 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c bandwidth.full = dfixed_mul(bandwidth, wm->vsc); wm 884 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static u32 dce_v10_0_latency_watermark(struct dce10_wm_params *wm) wm 888 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 available_bandwidth = dce_v10_0_available_bandwidth(wm); wm 891 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ wm 892 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + wm 893 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c (wm->num_heads * cursor_line_pair_return_time); wm 899 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (wm->num_heads == 0) wm 904 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if ((wm->vsc.full > a.full) || wm 905 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || wm 906 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c (wm->vtaps >= 5) || wm 907 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c ((wm->vsc.full >= a.full) && wm->interlaced)) wm 913 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b.full = dfixed_const(wm->num_heads); wm 915 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); wm 918 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); wm 920 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); wm 927 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (line_fill_time < wm->active_time) wm 930 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c return latency + (line_fill_time - wm->active_time); wm 945 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static bool dce_v10_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) wm 947 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (dce_v10_0_average_bandwidth(wm) <= wm 948 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c (dce_v10_0_dram_bandwidth_for_display(wm) / wm->num_heads)) wm 965 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static bool dce_v10_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) wm 967 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (dce_v10_0_average_bandwidth(wm) <= wm 968 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c (dce_v10_0_available_bandwidth(wm) / wm->num_heads)) wm 983 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c static bool dce_v10_0_check_latency_hiding(struct dce10_wm_params *wm) wm 985 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 lb_partitions = wm->lb_size / wm->src_width; wm 986 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c u32 line_time = wm->active_time + wm->blank_time; wm 992 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (wm->vsc.full > a.full) wm 995 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (lb_partitions <= (wm->vtaps + 1)) wm 1001 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); wm 1003 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c if (dce_v10_0_latency_watermark(wm) <= latency_hiding) wm 740 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm) wm 748 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c yclk.full = dfixed_const(wm->yclk); wm 750 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 769 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm) wm 777 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c yclk.full = dfixed_const(wm->yclk); wm 779 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 798 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm) wm 806 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c sclk.full = dfixed_const(wm->sclk); wm 827 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm) wm 835 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c disp_clk.full = dfixed_const(wm->disp_clk); wm 858 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm) wm 861 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm); wm 862 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm); wm 863 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm); wm 877 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm) wm 890 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c line_time.full = dfixed_const(wm->active_time + wm->blank_time); wm 892 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c bpp.full = dfixed_const(wm->bytes_per_pixel); wm 893 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c src_width.full = dfixed_const(wm->src_width); wm 895 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c bandwidth.full = dfixed_mul(bandwidth, wm->vsc); wm 910 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm) wm 914 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 available_bandwidth = dce_v11_0_available_bandwidth(wm); wm 917 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ wm 918 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + wm 919 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c (wm->num_heads * cursor_line_pair_return_time); wm 925 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (wm->num_heads == 0) wm 930 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if ((wm->vsc.full > a.full) || wm 931 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || wm 932 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c (wm->vtaps >= 5) || wm 933 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c ((wm->vsc.full >= a.full) && wm->interlaced)) wm 939 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b.full = dfixed_const(wm->num_heads); wm 941 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); wm 944 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); wm 946 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); wm 953 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (line_fill_time < wm->active_time) wm 956 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c return latency + (line_fill_time - wm->active_time); wm 971 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm) wm 973 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (dce_v11_0_average_bandwidth(wm) <= wm 974 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads)) wm 991 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm) wm 993 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (dce_v11_0_average_bandwidth(wm) <= wm 994 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c (dce_v11_0_available_bandwidth(wm) / wm->num_heads)) wm 1009 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm) wm 1011 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 lb_partitions = wm->lb_size / wm->src_width; wm 1012 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c u32 line_time = wm->active_time + wm->blank_time; wm 1018 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (wm->vsc.full > a.full) wm 1021 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (lb_partitions <= (wm->vtaps + 1)) wm 1027 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); wm 1029 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c if (dce_v11_0_latency_watermark(wm) <= latency_hiding) wm 513 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static u32 dce_v6_0_dram_bandwidth(struct dce6_wm_params *wm) wm 521 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c yclk.full = dfixed_const(wm->yclk); wm 523 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 542 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static u32 dce_v6_0_dram_bandwidth_for_display(struct dce6_wm_params *wm) wm 550 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c yclk.full = dfixed_const(wm->yclk); wm 552 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 571 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static u32 dce_v6_0_data_return_bandwidth(struct dce6_wm_params *wm) wm 579 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c sclk.full = dfixed_const(wm->sclk); wm 600 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static u32 dce_v6_0_dmif_request_bandwidth(struct dce6_wm_params *wm) wm 608 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c disp_clk.full = dfixed_const(wm->disp_clk); wm 631 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static u32 dce_v6_0_available_bandwidth(struct dce6_wm_params *wm) wm 634 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 dram_bandwidth = dce_v6_0_dram_bandwidth(wm); wm 635 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 data_return_bandwidth = dce_v6_0_data_return_bandwidth(wm); wm 636 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 dmif_req_bandwidth = dce_v6_0_dmif_request_bandwidth(wm); wm 650 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static u32 dce_v6_0_average_bandwidth(struct dce6_wm_params *wm) wm 663 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c line_time.full = dfixed_const(wm->active_time + wm->blank_time); wm 665 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c bpp.full = dfixed_const(wm->bytes_per_pixel); wm 666 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c src_width.full = dfixed_const(wm->src_width); wm 668 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c bandwidth.full = dfixed_mul(bandwidth, wm->vsc); wm 683 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static u32 dce_v6_0_latency_watermark(struct dce6_wm_params *wm) wm 687 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 available_bandwidth = dce_v6_0_available_bandwidth(wm); wm 690 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ wm 691 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + wm 692 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c (wm->num_heads * cursor_line_pair_return_time); wm 698 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (wm->num_heads == 0) wm 703 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if ((wm->vsc.full > a.full) || wm 704 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || wm 705 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c (wm->vtaps >= 5) || wm 706 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c ((wm->vsc.full >= a.full) && wm->interlaced)) wm 712 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b.full = dfixed_const(wm->num_heads); wm 714 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); wm 717 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); wm 719 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); wm 726 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (line_fill_time < wm->active_time) wm 729 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c return latency + (line_fill_time - wm->active_time); wm 744 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static bool dce_v6_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) wm 746 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (dce_v6_0_average_bandwidth(wm) <= wm 747 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c (dce_v6_0_dram_bandwidth_for_display(wm) / wm->num_heads)) wm 764 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static bool dce_v6_0_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) wm 766 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (dce_v6_0_average_bandwidth(wm) <= wm 767 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c (dce_v6_0_available_bandwidth(wm) / wm->num_heads)) wm 782 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c static bool dce_v6_0_check_latency_hiding(struct dce6_wm_params *wm) wm 784 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 lb_partitions = wm->lb_size / wm->src_width; wm 785 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c u32 line_time = wm->active_time + wm->blank_time; wm 791 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (wm->vsc.full > a.full) wm 794 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (lb_partitions <= (wm->vtaps + 1)) wm 800 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); wm 802 drivers/gpu/drm/amd/amdgpu/dce_v6_0.c if (dce_v6_0_latency_watermark(wm) <= latency_hiding) wm 649 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static u32 dce_v8_0_dram_bandwidth(struct dce8_wm_params *wm) wm 657 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c yclk.full = dfixed_const(wm->yclk); wm 659 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 678 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static u32 dce_v8_0_dram_bandwidth_for_display(struct dce8_wm_params *wm) wm 686 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c yclk.full = dfixed_const(wm->yclk); wm 688 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 707 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static u32 dce_v8_0_data_return_bandwidth(struct dce8_wm_params *wm) wm 715 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c sclk.full = dfixed_const(wm->sclk); wm 736 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static u32 dce_v8_0_dmif_request_bandwidth(struct dce8_wm_params *wm) wm 744 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c disp_clk.full = dfixed_const(wm->disp_clk); wm 767 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static u32 dce_v8_0_available_bandwidth(struct dce8_wm_params *wm) wm 770 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 dram_bandwidth = dce_v8_0_dram_bandwidth(wm); wm 771 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 data_return_bandwidth = dce_v8_0_data_return_bandwidth(wm); wm 772 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 dmif_req_bandwidth = dce_v8_0_dmif_request_bandwidth(wm); wm 786 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static u32 dce_v8_0_average_bandwidth(struct dce8_wm_params *wm) wm 799 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c line_time.full = dfixed_const(wm->active_time + wm->blank_time); wm 801 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c bpp.full = dfixed_const(wm->bytes_per_pixel); wm 802 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c src_width.full = dfixed_const(wm->src_width); wm 804 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c bandwidth.full = dfixed_mul(bandwidth, wm->vsc); wm 819 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static u32 dce_v8_0_latency_watermark(struct dce8_wm_params *wm) wm 823 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 available_bandwidth = dce_v8_0_available_bandwidth(wm); wm 826 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ wm 827 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + wm 828 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c (wm->num_heads * cursor_line_pair_return_time); wm 834 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (wm->num_heads == 0) wm 839 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if ((wm->vsc.full > a.full) || wm 840 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || wm 841 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c (wm->vtaps >= 5) || wm 842 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c ((wm->vsc.full >= a.full) && wm->interlaced)) wm 848 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b.full = dfixed_const(wm->num_heads); wm 850 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); wm 853 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); wm 855 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); wm 862 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (line_fill_time < wm->active_time) wm 865 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c return latency + (line_fill_time - wm->active_time); wm 880 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static bool dce_v8_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm) wm 882 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (dce_v8_0_average_bandwidth(wm) <= wm 883 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c (dce_v8_0_dram_bandwidth_for_display(wm) / wm->num_heads)) wm 900 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static bool dce_v8_0_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm) wm 902 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (dce_v8_0_average_bandwidth(wm) <= wm 903 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c (dce_v8_0_available_bandwidth(wm) / wm->num_heads)) wm 918 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c static bool dce_v8_0_check_latency_hiding(struct dce8_wm_params *wm) wm 920 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 lb_partitions = wm->lb_size / wm->src_width; wm 921 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c u32 line_time = wm->active_time + wm->blank_time; wm 927 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (wm->vsc.full > a.full) wm 930 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (lb_partitions <= (wm->vtaps + 1)) wm 936 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); wm 938 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c if (dce_v8_0_latency_watermark(wm) <= latency_hiding) wm 45 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c struct dcn_hubbub_wm *wm) wm 50 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c memset(wm, 0, sizeof(struct dcn_hubbub_wm)); wm 52 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s = &wm->sets[0]; wm 62 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s = &wm->sets[1]; wm 72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s = &wm->sets[2]; wm 82 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.c s = &wm->sets[3]; wm 333 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubbub.h struct dcn_hubbub_wm *wm); wm 101 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c struct dcn_hubbub_wm wm; wm 104 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c memset(&wm, 0, sizeof(struct dcn_hubbub_wm)); wm 105 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); wm 113 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c s = &wm.sets[i]; wm 74 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c struct dcn_hubbub_wm wm; wm 83 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c memset(&wm, 0, sizeof(struct dcn_hubbub_wm)); wm 84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dc->res_pool->hubbub->funcs->wm_read_state(dc->res_pool->hubbub, &wm); wm 93 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c s = &wm.sets[i]; wm 477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c struct dcn_hubbub_wm *wm) wm 483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c memset(wm, 0, sizeof(struct dcn_hubbub_wm)); wm 485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s = &wm->sets[0]; wm 496 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s = &wm->sets[1]; wm 507 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s = &wm->sets[2]; wm 518 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c s = &wm->sets[3]; wm 123 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.h struct dcn_hubbub_wm *wm); wm 513 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c struct dcn_hubbub_wm *wm) wm 518 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c memset(wm, 0, sizeof(struct dcn_hubbub_wm)); wm 520 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c s = &wm->sets[0]; wm 534 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c s = &wm->sets[1]; wm 548 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c s = &wm->sets[2]; wm 562 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.c s = &wm->sets[3]; wm 124 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubbub.h struct dcn_hubbub_wm *wm); wm 135 drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h struct dcn_hubbub_wm *wm); wm 205 drivers/gpu/drm/i915/display/intel_atomic.c crtc_state->wm.need_postvbl_update = false; wm 248 drivers/gpu/drm/i915/display/intel_atomic_plane.c if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id], wm 251 drivers/gpu/drm/i915/display/intel_atomic_plane.c skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_uv[plane_id], wm 257 drivers/gpu/drm/i915/display/intel_atomic_plane.c entries_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id]; wm 258 drivers/gpu/drm/i915/display/intel_atomic_plane.c entries_uv[plane_id] = crtc_state->wm.skl.plane_ddb_uv[plane_id]; wm 310 drivers/gpu/drm/i915/display/intel_atomic_plane.c memcpy(entries_y, old_crtc_state->wm.skl.plane_ddb_y, wm 311 drivers/gpu/drm/i915/display/intel_atomic_plane.c sizeof(old_crtc_state->wm.skl.plane_ddb_y)); wm 312 drivers/gpu/drm/i915/display/intel_atomic_plane.c memcpy(entries_uv, old_crtc_state->wm.skl.plane_ddb_uv, wm 313 drivers/gpu/drm/i915/display/intel_atomic_plane.c sizeof(old_crtc_state->wm.skl.plane_ddb_uv)); wm 12262 drivers/gpu/drm/i915/display/intel_display.c saved_state->wm = crtc_state->wm; wm 12883 drivers/gpu/drm/i915/display/intel_display.c struct skl_pipe_wm wm; wm 12898 drivers/gpu/drm/i915/display/intel_display.c skl_pipe_wm_get_hw_state(crtc, &hw->wm); wm 12899 drivers/gpu/drm/i915/display/intel_display.c sw_wm = &new_crtc_state->wm.skl.optimal; wm 12904 drivers/gpu/drm/i915/display/intel_display.c sw_ddb = &dev_priv->wm.skl_hw.ddb; wm 12916 drivers/gpu/drm/i915/display/intel_display.c hw_plane_wm = &hw->wm.planes[plane]; wm 12921 drivers/gpu/drm/i915/display/intel_display.c if (skl_wm_level_equals(&hw_plane_wm->wm[level], wm 12922 drivers/gpu/drm/i915/display/intel_display.c &sw_plane_wm->wm[level])) wm 12927 drivers/gpu/drm/i915/display/intel_display.c sw_plane_wm->wm[level].plane_en, wm 12928 drivers/gpu/drm/i915/display/intel_display.c sw_plane_wm->wm[level].plane_res_b, wm 12929 drivers/gpu/drm/i915/display/intel_display.c sw_plane_wm->wm[level].plane_res_l, wm 12930 drivers/gpu/drm/i915/display/intel_display.c hw_plane_wm->wm[level].plane_en, wm 12931 drivers/gpu/drm/i915/display/intel_display.c hw_plane_wm->wm[level].plane_res_b, wm 12932 drivers/gpu/drm/i915/display/intel_display.c hw_plane_wm->wm[level].plane_res_l); wm 12949 drivers/gpu/drm/i915/display/intel_display.c sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[plane]; wm 12968 drivers/gpu/drm/i915/display/intel_display.c hw_plane_wm = &hw->wm.planes[PLANE_CURSOR]; wm 12973 drivers/gpu/drm/i915/display/intel_display.c if (skl_wm_level_equals(&hw_plane_wm->wm[level], wm 12974 drivers/gpu/drm/i915/display/intel_display.c &sw_plane_wm->wm[level])) wm 12979 drivers/gpu/drm/i915/display/intel_display.c sw_plane_wm->wm[level].plane_en, wm 12980 drivers/gpu/drm/i915/display/intel_display.c sw_plane_wm->wm[level].plane_res_b, wm 12981 drivers/gpu/drm/i915/display/intel_display.c sw_plane_wm->wm[level].plane_res_l, wm 12982 drivers/gpu/drm/i915/display/intel_display.c hw_plane_wm->wm[level].plane_en, wm 12983 drivers/gpu/drm/i915/display/intel_display.c hw_plane_wm->wm[level].plane_res_b, wm 12984 drivers/gpu/drm/i915/display/intel_display.c hw_plane_wm->wm[level].plane_res_l); wm 13001 drivers/gpu/drm/i915/display/intel_display.c sw_ddb_entry = &new_crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; wm 13796 drivers/gpu/drm/i915/display/intel_display.c u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; wm 13803 drivers/gpu/drm/i915/display/intel_display.c entries[i] = old_crtc_state->wm.skl.ddb; wm 13827 drivers/gpu/drm/i915/display/intel_display.c if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb, wm 13833 drivers/gpu/drm/i915/display/intel_display.c entries[i] = new_crtc_state->wm.skl.ddb; wm 13841 drivers/gpu/drm/i915/display/intel_display.c if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb, wm 13842 drivers/gpu/drm/i915/display/intel_display.c &old_crtc_state->wm.skl.ddb) && wm 14188 drivers/gpu/drm/i915/display/intel_display.c if (new_crtc_state->wm.need_postvbl_update || wm 14212 drivers/gpu/drm/i915/display/intel_display.c dev_priv->wm.distrust_bios_wm = false; wm 16043 drivers/gpu/drm/i915/display/intel_display.c crtc_state->wm.need_postvbl_update = true; wm 16046 drivers/gpu/drm/i915/display/intel_display.c to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm; wm 4148 drivers/gpu/drm/i915/display/intel_display_power.c const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices; wm 4165 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices; wm 4184 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->wm.skl_hw.ddb.enabled_slices = 1; wm 4203 drivers/gpu/drm/i915/display/intel_display_power.c dev_priv->wm.skl_hw.ddb.enabled_slices = 1; wm 626 drivers/gpu/drm/i915/display/intel_display_types.h struct intel_wm_level wm[5]; wm 635 drivers/gpu/drm/i915/display/intel_display_types.h struct skl_wm_level wm[8]; wm 654 drivers/gpu/drm/i915/display/intel_display_types.h struct g4x_pipe_wm wm[NUM_VLV_WM_LEVELS]; wm 672 drivers/gpu/drm/i915/display/intel_display_types.h struct g4x_pipe_wm wm; wm 927 drivers/gpu/drm/i915/display/intel_display_types.h struct intel_crtc_wm_state wm; wm 1017 drivers/gpu/drm/i915/display/intel_display_types.h } wm; wm 2936 drivers/gpu/drm/i915/i915_debugfs.c dev_priv->wm.distrust_bios_wm = true; wm 2976 drivers/gpu/drm/i915/i915_debugfs.c entry = &crtc_state->wm.skl.plane_ddb_y[plane_id]; wm 2982 drivers/gpu/drm/i915/i915_debugfs.c entry = &crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR]; wm 3307 drivers/gpu/drm/i915/i915_debugfs.c static void wm_latency_show(struct seq_file *m, const u16 wm[8]) wm 3326 drivers/gpu/drm/i915/i915_debugfs.c unsigned int latency = wm[level]; wm 3341 drivers/gpu/drm/i915/i915_debugfs.c level, wm[level], latency / 10, latency % 10); wm 3353 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; wm 3355 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.pri_latency; wm 3368 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; wm 3370 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.spr_latency; wm 3383 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; wm 3385 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.cur_latency; wm 3423 drivers/gpu/drm/i915/i915_debugfs.c size_t len, loff_t *offp, u16 wm[8]) wm 3460 drivers/gpu/drm/i915/i915_debugfs.c wm[level] = new[level]; wm 3476 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; wm 3478 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.pri_latency; wm 3491 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; wm 3493 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.spr_latency; wm 3506 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.skl_latency; wm 3508 drivers/gpu/drm/i915/i915_debugfs.c latencies = dev_priv->wm.cur_latency; wm 582 drivers/gpu/drm/i915/i915_drv.c mutex_init(&dev_priv->wm.wm_mutex); wm 1619 drivers/gpu/drm/i915/i915_drv.h } wm; wm 174 drivers/gpu/drm/i915/i915_trace.h TP_PROTO(struct intel_crtc *crtc, const struct g4x_wm_values *wm), wm 175 drivers/gpu/drm/i915/i915_trace.h TP_ARGS(crtc, wm), wm 199 drivers/gpu/drm/i915/i915_trace.h __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; wm 200 drivers/gpu/drm/i915/i915_trace.h __entry->sprite = wm->pipe[crtc->pipe].plane[PLANE_SPRITE0]; wm 201 drivers/gpu/drm/i915/i915_trace.h __entry->cursor = wm->pipe[crtc->pipe].plane[PLANE_CURSOR]; wm 202 drivers/gpu/drm/i915/i915_trace.h __entry->sr_plane = wm->sr.plane; wm 203 drivers/gpu/drm/i915/i915_trace.h __entry->sr_cursor = wm->sr.cursor; wm 204 drivers/gpu/drm/i915/i915_trace.h __entry->sr_fbc = wm->sr.fbc; wm 205 drivers/gpu/drm/i915/i915_trace.h __entry->hpll_plane = wm->hpll.plane; wm 206 drivers/gpu/drm/i915/i915_trace.h __entry->hpll_cursor = wm->hpll.cursor; wm 207 drivers/gpu/drm/i915/i915_trace.h __entry->hpll_fbc = wm->hpll.fbc; wm 208 drivers/gpu/drm/i915/i915_trace.h __entry->cxsr = wm->cxsr; wm 209 drivers/gpu/drm/i915/i915_trace.h __entry->hpll = wm->hpll_en; wm 210 drivers/gpu/drm/i915/i915_trace.h __entry->fbc = wm->fbc_en; wm 222 drivers/gpu/drm/i915/i915_trace.h TP_PROTO(struct intel_crtc *crtc, const struct vlv_wm_values *wm), wm 223 drivers/gpu/drm/i915/i915_trace.h TP_ARGS(crtc, wm), wm 243 drivers/gpu/drm/i915/i915_trace.h __entry->level = wm->level; wm 244 drivers/gpu/drm/i915/i915_trace.h __entry->cxsr = wm->cxsr; wm 245 drivers/gpu/drm/i915/i915_trace.h __entry->primary = wm->pipe[crtc->pipe].plane[PLANE_PRIMARY]; wm 246 drivers/gpu/drm/i915/i915_trace.h __entry->sprite0 = wm->pipe[crtc->pipe].plane[PLANE_SPRITE0]; wm 247 drivers/gpu/drm/i915/i915_trace.h __entry->sprite1 = wm->pipe[crtc->pipe].plane[PLANE_SPRITE1]; wm 248 drivers/gpu/drm/i915/i915_trace.h __entry->cursor = wm->pipe[crtc->pipe].plane[PLANE_CURSOR]; wm 249 drivers/gpu/drm/i915/i915_trace.h __entry->sr_plane = wm->sr.plane; wm 250 drivers/gpu/drm/i915/i915_trace.h __entry->sr_cursor = wm->sr.cursor; wm 463 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 466 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.vlv.cxsr = enable; wm 468 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.g4x.cxsr = enable; wm 469 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 497 drivers/gpu/drm/i915/intel_pm.c struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; wm 768 drivers/gpu/drm/i915/intel_pm.c const struct intel_watermark_params *wm, wm 782 drivers/gpu/drm/i915/intel_pm.c entries = DIV_ROUND_UP(entries, wm->cacheline_size) + wm 783 drivers/gpu/drm/i915/intel_pm.c wm->guard_size; wm 790 drivers/gpu/drm/i915/intel_pm.c if (wm_size > wm->max_wm) wm 791 drivers/gpu/drm/i915/intel_pm.c wm_size = wm->max_wm; wm 793 drivers/gpu/drm/i915/intel_pm.c wm_size = wm->default_wm; wm 820 drivers/gpu/drm/i915/intel_pm.c return dev_priv->wm.max_level + 1; wm 867 drivers/gpu/drm/i915/intel_pm.c unsigned int wm; wm 889 drivers/gpu/drm/i915/intel_pm.c wm = intel_calculate_wm(clock, &pineview_display_wm, wm 894 drivers/gpu/drm/i915/intel_pm.c reg |= FW_WM(wm, SR); wm 899 drivers/gpu/drm/i915/intel_pm.c wm = intel_calculate_wm(clock, &pineview_cursor_wm, wm 904 drivers/gpu/drm/i915/intel_pm.c reg |= FW_WM(wm, CURSOR_SR); wm 908 drivers/gpu/drm/i915/intel_pm.c wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, wm 913 drivers/gpu/drm/i915/intel_pm.c reg |= FW_WM(wm, HPLL_SR); wm 917 drivers/gpu/drm/i915/intel_pm.c wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, wm 922 drivers/gpu/drm/i915/intel_pm.c reg |= FW_WM(wm, HPLL_CURSOR); wm 950 drivers/gpu/drm/i915/intel_pm.c const struct g4x_wm_values *wm) wm 955 drivers/gpu/drm/i915/intel_pm.c trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); wm 958 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->sr.plane, SR) | wm 959 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | wm 960 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | wm 961 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); wm 963 drivers/gpu/drm/i915/intel_pm.c (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) | wm 964 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->sr.fbc, FBC_SR) | wm 965 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->hpll.fbc, FBC_HPLL_SR) | wm 966 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | wm 967 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | wm 968 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); wm 970 drivers/gpu/drm/i915/intel_pm.c (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) | wm 971 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->sr.cursor, CURSOR_SR) | wm 972 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->hpll.cursor, HPLL_CURSOR) | wm 973 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->hpll.plane, HPLL_SR)); wm 982 drivers/gpu/drm/i915/intel_pm.c const struct vlv_wm_values *wm) wm 987 drivers/gpu/drm/i915/intel_pm.c trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); wm 990 drivers/gpu/drm/i915/intel_pm.c (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) | wm 991 drivers/gpu/drm/i915/intel_pm.c (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) | wm 992 drivers/gpu/drm/i915/intel_pm.c (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) | wm 993 drivers/gpu/drm/i915/intel_pm.c (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT)); wm 1008 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->sr.plane, SR) | wm 1009 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | wm 1010 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | wm 1011 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); wm 1013 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | wm 1014 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | wm 1015 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); wm 1017 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->sr.cursor, CURSOR_SR)); wm 1021 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | wm 1022 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); wm 1024 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | wm 1025 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); wm 1027 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | wm 1028 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); wm 1030 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->sr.plane >> 9, SR_HI) | wm 1031 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | wm 1032 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | wm 1033 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | wm 1034 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | wm 1035 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | wm 1036 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | wm 1037 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | wm 1038 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | wm 1039 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); wm 1042 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | wm 1043 drivers/gpu/drm/i915/intel_pm.c FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); wm 1045 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->sr.plane >> 9, SR_HI) | wm 1046 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | wm 1047 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | wm 1048 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | wm 1049 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | wm 1050 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | wm 1051 drivers/gpu/drm/i915/intel_pm.c FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); wm 1062 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; wm 1063 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12; wm 1064 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35; wm 1066 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL; wm 1119 drivers/gpu/drm/i915/intel_pm.c unsigned int latency = dev_priv->wm.pri_latency[level] * 10; wm 1120 drivers/gpu/drm/i915/intel_pm.c unsigned int clock, htotal, cpp, width, wm; wm 1154 drivers/gpu/drm/i915/intel_pm.c wm = intel_wm_method2(clock, htotal, width, cpp, latency); wm 1157 drivers/gpu/drm/i915/intel_pm.c wm = intel_wm_method1(clock, cpp, latency); wm 1164 drivers/gpu/drm/i915/intel_pm.c wm = min(small, large); wm 1167 drivers/gpu/drm/i915/intel_pm.c wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level), wm 1170 drivers/gpu/drm/i915/intel_pm.c wm = DIV_ROUND_UP(wm, 64) + 2; wm 1172 drivers/gpu/drm/i915/intel_pm.c return min_t(unsigned int, wm, USHRT_MAX); wm 1182 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; wm 1201 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; wm 1231 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; wm 1232 drivers/gpu/drm/i915/intel_pm.c int wm, max_wm; wm 1234 drivers/gpu/drm/i915/intel_pm.c wm = g4x_compute_wm(crtc_state, plane_state, level); wm 1237 drivers/gpu/drm/i915/intel_pm.c if (wm > max_wm) wm 1240 drivers/gpu/drm/i915/intel_pm.c dirty |= raw->plane[plane_id] != wm; wm 1241 drivers/gpu/drm/i915/intel_pm.c raw->plane[plane_id] = wm; wm 1247 drivers/gpu/drm/i915/intel_pm.c wm = ilk_compute_fbc_wm(crtc_state, plane_state, wm 1255 drivers/gpu/drm/i915/intel_pm.c if (wm > max_wm) wm 1256 drivers/gpu/drm/i915/intel_pm.c wm = USHRT_MAX; wm 1258 drivers/gpu/drm/i915/intel_pm.c dirty |= raw->fbc != wm; wm 1259 drivers/gpu/drm/i915/intel_pm.c raw->fbc = wm; wm 1272 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], wm 1273 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], wm 1274 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); wm 1278 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, wm 1279 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); wm 1288 drivers/gpu/drm/i915/intel_pm.c const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; wm 1298 drivers/gpu/drm/i915/intel_pm.c if (level > dev_priv->wm.max_level) wm 1314 drivers/gpu/drm/i915/intel_pm.c wm_state->wm.plane[plane_id] = USHRT_MAX; wm 1337 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; wm 1366 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; wm 1368 drivers/gpu/drm/i915/intel_pm.c wm_state->wm.plane[plane_id] = raw->plane[plane_id]; wm 1375 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; wm 1387 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; wm 1424 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate; wm 1425 drivers/gpu/drm/i915/intel_pm.c const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal; wm 1430 drivers/gpu/drm/i915/intel_pm.c const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal; wm 1448 drivers/gpu/drm/i915/intel_pm.c intermediate->wm.plane[plane_id] = wm 1449 drivers/gpu/drm/i915/intel_pm.c max(optimal->wm.plane[plane_id], wm 1450 drivers/gpu/drm/i915/intel_pm.c active->wm.plane[plane_id]); wm 1452 drivers/gpu/drm/i915/intel_pm.c WARN_ON(intermediate->wm.plane[plane_id] > wm 1492 drivers/gpu/drm/i915/intel_pm.c new_crtc_state->wm.need_postvbl_update = true; wm 1498 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_values *wm) wm 1503 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = true; wm 1504 drivers/gpu/drm/i915/intel_pm.c wm->hpll_en = true; wm 1505 drivers/gpu/drm/i915/intel_pm.c wm->fbc_en = true; wm 1508 drivers/gpu/drm/i915/intel_pm.c const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; wm 1514 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = false; wm 1516 drivers/gpu/drm/i915/intel_pm.c wm->hpll_en = false; wm 1518 drivers/gpu/drm/i915/intel_pm.c wm->fbc_en = false; wm 1524 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = false; wm 1525 drivers/gpu/drm/i915/intel_pm.c wm->hpll_en = false; wm 1526 drivers/gpu/drm/i915/intel_pm.c wm->fbc_en = false; wm 1530 drivers/gpu/drm/i915/intel_pm.c const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; wm 1533 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe] = wm_state->wm; wm 1534 drivers/gpu/drm/i915/intel_pm.c if (crtc->active && wm->cxsr) wm 1535 drivers/gpu/drm/i915/intel_pm.c wm->sr = wm_state->sr; wm 1536 drivers/gpu/drm/i915/intel_pm.c if (crtc->active && wm->hpll_en) wm 1537 drivers/gpu/drm/i915/intel_pm.c wm->hpll = wm_state->hpll; wm 1543 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_values *old_wm = &dev_priv->wm.g4x; wm 1568 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 1569 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; wm 1571 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 1580 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->wm.need_postvbl_update) wm 1583 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 1584 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; wm 1586 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 1608 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; wm 1610 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; wm 1613 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; wm 1614 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; wm 1616 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; wm 1628 drivers/gpu/drm/i915/intel_pm.c unsigned int clock, htotal, cpp, width, wm; wm 1630 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->wm.pri_latency[level] == 0) wm 1648 drivers/gpu/drm/i915/intel_pm.c wm = 63; wm 1650 drivers/gpu/drm/i915/intel_pm.c wm = vlv_wm_method2(clock, htotal, width, cpp, wm 1651 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[level] * 10); wm 1654 drivers/gpu/drm/i915/intel_pm.c return min_t(unsigned int, wm, USHRT_MAX); wm 1667 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; wm 1668 drivers/gpu/drm/i915/intel_pm.c struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; wm 1755 drivers/gpu/drm/i915/intel_pm.c wm_state->wm[level].plane[plane_id] = USHRT_MAX; wm 1762 drivers/gpu/drm/i915/intel_pm.c static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size) wm 1764 drivers/gpu/drm/i915/intel_pm.c if (wm > fifo_size) wm 1767 drivers/gpu/drm/i915/intel_pm.c return fifo_size - wm; wm 1782 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; wm 1806 drivers/gpu/drm/i915/intel_pm.c struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; wm 1807 drivers/gpu/drm/i915/intel_pm.c int wm = vlv_compute_wm_level(crtc_state, plane_state, level); wm 1810 drivers/gpu/drm/i915/intel_pm.c if (wm > max_wm) wm 1813 drivers/gpu/drm/i915/intel_pm.c dirty |= raw->plane[plane_id] != wm; wm 1814 drivers/gpu/drm/i915/intel_pm.c raw->plane[plane_id] = wm; wm 1824 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], wm 1825 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], wm 1826 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); wm 1835 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.raw[level]; wm 1837 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; wm 1856 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; wm 1858 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; wm 1897 drivers/gpu/drm/i915/intel_pm.c &old_crtc_state->wm.vlv.fifo_state; wm 1919 drivers/gpu/drm/i915/intel_pm.c const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; wm 1926 drivers/gpu/drm/i915/intel_pm.c wm_state->wm[level].plane[plane_id] = wm 1964 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; wm 2057 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate; wm 2058 drivers/gpu/drm/i915/intel_pm.c const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal; wm 2063 drivers/gpu/drm/i915/intel_pm.c const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal; wm 2081 drivers/gpu/drm/i915/intel_pm.c intermediate->wm[level].plane[plane_id] = wm 2082 drivers/gpu/drm/i915/intel_pm.c min(optimal->wm[level].plane[plane_id], wm 2083 drivers/gpu/drm/i915/intel_pm.c active->wm[level].plane[plane_id]); wm 2100 drivers/gpu/drm/i915/intel_pm.c new_crtc_state->wm.need_postvbl_update = true; wm 2106 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_values *wm) wm 2111 drivers/gpu/drm/i915/intel_pm.c wm->level = dev_priv->wm.max_level; wm 2112 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = true; wm 2115 drivers/gpu/drm/i915/intel_pm.c const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; wm 2121 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = false; wm 2124 drivers/gpu/drm/i915/intel_pm.c wm->level = min_t(int, wm->level, wm_state->num_levels - 1); wm 2128 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = false; wm 2131 drivers/gpu/drm/i915/intel_pm.c wm->level = VLV_WM_LEVEL_PM2; wm 2134 drivers/gpu/drm/i915/intel_pm.c const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; wm 2137 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe] = wm_state->wm[wm->level]; wm 2138 drivers/gpu/drm/i915/intel_pm.c if (crtc->active && wm->cxsr) wm 2139 drivers/gpu/drm/i915/intel_pm.c wm->sr = wm_state->sr[wm->level]; wm 2141 drivers/gpu/drm/i915/intel_pm.c wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2; wm 2142 drivers/gpu/drm/i915/intel_pm.c wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2; wm 2143 drivers/gpu/drm/i915/intel_pm.c wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2; wm 2144 drivers/gpu/drm/i915/intel_pm.c wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2; wm 2150 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_values *old_wm = &dev_priv->wm.vlv; wm 2187 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 2188 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; wm 2190 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 2199 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->wm.need_postvbl_update) wm 2202 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 2203 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; wm 2205 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 2770 drivers/gpu/drm/i915/intel_pm.c u16 pri_latency = dev_priv->wm.pri_latency[level]; wm 2771 drivers/gpu/drm/i915/intel_pm.c u16 spr_latency = dev_priv->wm.spr_latency[level]; wm 2772 drivers/gpu/drm/i915/intel_pm.c u16 cur_latency = dev_priv->wm.cur_latency[level]; wm 2825 drivers/gpu/drm/i915/intel_pm.c u16 wm[8]) wm 2845 drivers/gpu/drm/i915/intel_pm.c wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; wm 2846 drivers/gpu/drm/i915/intel_pm.c wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & wm 2848 drivers/gpu/drm/i915/intel_pm.c wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & wm 2850 drivers/gpu/drm/i915/intel_pm.c wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & wm 2863 drivers/gpu/drm/i915/intel_pm.c wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; wm 2864 drivers/gpu/drm/i915/intel_pm.c wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & wm 2866 drivers/gpu/drm/i915/intel_pm.c wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & wm 2868 drivers/gpu/drm/i915/intel_pm.c wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & wm 2877 drivers/gpu/drm/i915/intel_pm.c if (wm[level] == 0) { wm 2879 drivers/gpu/drm/i915/intel_pm.c wm[i] = 0; wm 2891 drivers/gpu/drm/i915/intel_pm.c if (wm[0] == 0) { wm 2892 drivers/gpu/drm/i915/intel_pm.c wm[0] += 2; wm 2894 drivers/gpu/drm/i915/intel_pm.c if (wm[level] == 0) wm 2896 drivers/gpu/drm/i915/intel_pm.c wm[level] += 2; wm 2907 drivers/gpu/drm/i915/intel_pm.c wm[0] += 1; wm 2912 drivers/gpu/drm/i915/intel_pm.c wm[0] = (sskpd >> 56) & 0xFF; wm 2913 drivers/gpu/drm/i915/intel_pm.c if (wm[0] == 0) wm 2914 drivers/gpu/drm/i915/intel_pm.c wm[0] = sskpd & 0xF; wm 2915 drivers/gpu/drm/i915/intel_pm.c wm[1] = (sskpd >> 4) & 0xFF; wm 2916 drivers/gpu/drm/i915/intel_pm.c wm[2] = (sskpd >> 12) & 0xFF; wm 2917 drivers/gpu/drm/i915/intel_pm.c wm[3] = (sskpd >> 20) & 0x1FF; wm 2918 drivers/gpu/drm/i915/intel_pm.c wm[4] = (sskpd >> 32) & 0x1FF; wm 2922 drivers/gpu/drm/i915/intel_pm.c wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; wm 2923 drivers/gpu/drm/i915/intel_pm.c wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; wm 2924 drivers/gpu/drm/i915/intel_pm.c wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; wm 2925 drivers/gpu/drm/i915/intel_pm.c wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; wm 2930 drivers/gpu/drm/i915/intel_pm.c wm[0] = 7; wm 2931 drivers/gpu/drm/i915/intel_pm.c wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; wm 2932 drivers/gpu/drm/i915/intel_pm.c wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; wm 2939 drivers/gpu/drm/i915/intel_pm.c u16 wm[5]) wm 2943 drivers/gpu/drm/i915/intel_pm.c wm[0] = 13; wm 2947 drivers/gpu/drm/i915/intel_pm.c u16 wm[5]) wm 2951 drivers/gpu/drm/i915/intel_pm.c wm[0] = 13; wm 2969 drivers/gpu/drm/i915/intel_pm.c const u16 wm[8]) wm 2974 drivers/gpu/drm/i915/intel_pm.c unsigned int latency = wm[level]; wm 2992 drivers/gpu/drm/i915/intel_pm.c name, level, wm[level], wm 2998 drivers/gpu/drm/i915/intel_pm.c u16 wm[5], u16 min) wm 3002 drivers/gpu/drm/i915/intel_pm.c if (wm[0] >= min) wm 3005 drivers/gpu/drm/i915/intel_pm.c wm[0] = max(wm[0], min); wm 3007 drivers/gpu/drm/i915/intel_pm.c wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5)); wm 3020 drivers/gpu/drm/i915/intel_pm.c changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | wm 3021 drivers/gpu/drm/i915/intel_pm.c ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | wm 3022 drivers/gpu/drm/i915/intel_pm.c ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); wm 3028 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); wm 3029 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); wm 3030 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); wm 3046 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->wm.pri_latency[3] == 0 && wm 3047 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.spr_latency[3] == 0 && wm 3048 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.cur_latency[3] == 0) wm 3051 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.pri_latency[3] = 0; wm 3052 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.spr_latency[3] = 0; wm 3053 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.cur_latency[3] = 0; wm 3056 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); wm 3057 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); wm 3058 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); wm 3063 drivers/gpu/drm/i915/intel_pm.c intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency); wm 3065 drivers/gpu/drm/i915/intel_pm.c memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, wm 3066 drivers/gpu/drm/i915/intel_pm.c sizeof(dev_priv->wm.pri_latency)); wm 3067 drivers/gpu/drm/i915/intel_pm.c memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, wm 3068 drivers/gpu/drm/i915/intel_pm.c sizeof(dev_priv->wm.pri_latency)); wm 3070 drivers/gpu/drm/i915/intel_pm.c intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency); wm 3071 drivers/gpu/drm/i915/intel_pm.c intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency); wm 3073 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); wm 3074 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); wm 3075 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); wm 3085 drivers/gpu/drm/i915/intel_pm.c intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency); wm 3086 drivers/gpu/drm/i915/intel_pm.c intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency); wm 3104 drivers/gpu/drm/i915/intel_pm.c if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { wm 3128 drivers/gpu/drm/i915/intel_pm.c pipe_wm = &crtc_state->wm.ilk.optimal; wm 3159 drivers/gpu/drm/i915/intel_pm.c memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm)); wm 3161 drivers/gpu/drm/i915/intel_pm.c pristate, sprstate, curstate, &pipe_wm->wm[0]); wm 3172 drivers/gpu/drm/i915/intel_pm.c struct intel_wm_level *wm = &pipe_wm->wm[level]; wm 3175 drivers/gpu/drm/i915/intel_pm.c pristate, sprstate, curstate, wm); wm 3182 drivers/gpu/drm/i915/intel_pm.c if (!ilk_validate_wm_level(level, &max, wm)) { wm 3183 drivers/gpu/drm/i915/intel_pm.c memset(wm, 0, sizeof(*wm)); wm 3200 drivers/gpu/drm/i915/intel_pm.c struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate; wm 3205 drivers/gpu/drm/i915/intel_pm.c const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal; wm 3213 drivers/gpu/drm/i915/intel_pm.c *a = newstate->wm.ilk.optimal; wm 3223 drivers/gpu/drm/i915/intel_pm.c struct intel_wm_level *a_wm = &a->wm[level]; wm 3224 drivers/gpu/drm/i915/intel_pm.c const struct intel_wm_level *b_wm = &b->wm[level]; wm 3246 drivers/gpu/drm/i915/intel_pm.c if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0) wm 3247 drivers/gpu/drm/i915/intel_pm.c newstate->wm.need_postvbl_update = true; wm 3264 drivers/gpu/drm/i915/intel_pm.c const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk; wm 3265 drivers/gpu/drm/i915/intel_pm.c const struct intel_wm_level *wm = &active->wm[level]; wm 3275 drivers/gpu/drm/i915/intel_pm.c if (!wm->enable) wm 3278 drivers/gpu/drm/i915/intel_pm.c ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); wm 3279 drivers/gpu/drm/i915/intel_pm.c ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); wm 3280 drivers/gpu/drm/i915/intel_pm.c ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); wm 3281 drivers/gpu/drm/i915/intel_pm.c ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); wm 3306 drivers/gpu/drm/i915/intel_pm.c struct intel_wm_level *wm = &merged->wm[level]; wm 3308 drivers/gpu/drm/i915/intel_pm.c ilk_merge_wm_level(dev_priv, level, wm); wm 3311 drivers/gpu/drm/i915/intel_pm.c wm->enable = false; wm 3312 drivers/gpu/drm/i915/intel_pm.c else if (!ilk_validate_wm_level(level, max, wm)) wm 3320 drivers/gpu/drm/i915/intel_pm.c if (wm->fbc_val > max->fbc) { wm 3321 drivers/gpu/drm/i915/intel_pm.c if (wm->enable) wm 3323 drivers/gpu/drm/i915/intel_pm.c wm->fbc_val = 0; wm 3336 drivers/gpu/drm/i915/intel_pm.c struct intel_wm_level *wm = &merged->wm[level]; wm 3338 drivers/gpu/drm/i915/intel_pm.c wm->enable = false; wm 3346 drivers/gpu/drm/i915/intel_pm.c return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); wm 3356 drivers/gpu/drm/i915/intel_pm.c return dev_priv->wm.pri_latency[level]; wm 3376 drivers/gpu/drm/i915/intel_pm.c r = &merged->wm[level]; wm 3412 drivers/gpu/drm/i915/intel_pm.c &intel_crtc->wm.active.ilk.wm[0]; wm 3417 drivers/gpu/drm/i915/intel_pm.c results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime; wm 3437 drivers/gpu/drm/i915/intel_pm.c if (r1->wm[level].enable) wm 3439 drivers/gpu/drm/i915/intel_pm.c if (r2->wm[level].enable) wm 3518 drivers/gpu/drm/i915/intel_pm.c struct ilk_wm_values *previous = &dev_priv->wm.hw; wm 3552 drivers/gpu/drm/i915/intel_pm.c struct ilk_wm_values *previous = &dev_priv->wm.hw; wm 3621 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.hw = *results; wm 3791 drivers/gpu/drm/i915/intel_pm.c struct skl_plane_wm *wm = wm 3792 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane->id]; wm 3795 drivers/gpu/drm/i915/intel_pm.c if (!wm->wm[0].plane_en) wm 3800 drivers/gpu/drm/i915/intel_pm.c !wm->wm[level].plane_en; --level) wm 3803 drivers/gpu/drm/i915/intel_pm.c latency = dev_priv->wm.skl_latency[level]; wm 3903 drivers/gpu/drm/i915/intel_pm.c *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; wm 3951 drivers/gpu/drm/i915/intel_pm.c struct skl_wm_level wm = {}; wm 3963 drivers/gpu/drm/i915/intel_pm.c skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm); wm 3964 drivers/gpu/drm/i915/intel_pm.c if (wm.min_ddb_alloc == U16_MAX) wm 3967 drivers/gpu/drm/i915/intel_pm.c min_ddb_alloc = wm.min_ddb_alloc; wm 4341 drivers/gpu/drm/i915/intel_pm.c struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb; wm 4354 drivers/gpu/drm/i915/intel_pm.c memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y)); wm 4355 drivers/gpu/drm/i915/intel_pm.c memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv)); wm 4385 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start = wm 4387 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end; wm 4399 drivers/gpu/drm/i915/intel_pm.c const struct skl_plane_wm *wm = wm 4400 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; wm 4403 drivers/gpu/drm/i915/intel_pm.c if (WARN_ON(wm->wm[level].min_ddb_alloc > wm 4411 drivers/gpu/drm/i915/intel_pm.c blocks += wm->wm[level].min_ddb_alloc; wm 4412 drivers/gpu/drm/i915/intel_pm.c blocks += wm->uv_wm[level].min_ddb_alloc; wm 4434 drivers/gpu/drm/i915/intel_pm.c const struct skl_plane_wm *wm = wm 4435 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; wm 4453 drivers/gpu/drm/i915/intel_pm.c total[plane_id] = wm->wm[level].min_ddb_alloc + extra; wm 4464 drivers/gpu/drm/i915/intel_pm.c uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra; wm 4474 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_y[plane_id]; wm 4476 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_uv[plane_id]; wm 4506 drivers/gpu/drm/i915/intel_pm.c struct skl_plane_wm *wm = wm 4507 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; wm 4521 drivers/gpu/drm/i915/intel_pm.c if (wm->wm[level].min_ddb_alloc > total[plane_id] || wm 4522 drivers/gpu/drm/i915/intel_pm.c wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id]) wm 4523 drivers/gpu/drm/i915/intel_pm.c memset(&wm->wm[level], 0, sizeof(wm->wm[level])); wm 4530 drivers/gpu/drm/i915/intel_pm.c level == 1 && wm->wm[0].plane_en) { wm 4531 drivers/gpu/drm/i915/intel_pm.c wm->wm[level].plane_res_b = wm->wm[0].plane_res_b; wm 4532 drivers/gpu/drm/i915/intel_pm.c wm->wm[level].plane_res_l = wm->wm[0].plane_res_l; wm 4533 drivers/gpu/drm/i915/intel_pm.c wm->wm[level].ignore_lines = wm->wm[0].ignore_lines; wm 4543 drivers/gpu/drm/i915/intel_pm.c struct skl_plane_wm *wm = wm 4544 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; wm 4546 drivers/gpu/drm/i915/intel_pm.c if (wm->trans_wm.plane_res_b >= total[plane_id]) wm 4547 drivers/gpu/drm/i915/intel_pm.c memset(&wm->trans_wm, 0, sizeof(wm->trans_wm)); wm 4772 drivers/gpu/drm/i915/intel_pm.c u32 latency = dev_priv->wm.skl_latency[level]; wm 4929 drivers/gpu/drm/i915/intel_pm.c struct skl_plane_wm *wm) wm 4961 drivers/gpu/drm/i915/intel_pm.c wm0_sel_res_b = wm->wm[0].plane_res_b - 1; wm 4982 drivers/gpu/drm/i915/intel_pm.c wm->trans_wm.plane_res_b = res_blocks + 1; wm 4983 drivers/gpu/drm/i915/intel_pm.c wm->trans_wm.plane_en = true; wm 4990 drivers/gpu/drm/i915/intel_pm.c struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; wm 4999 drivers/gpu/drm/i915/intel_pm.c skl_compute_wm_levels(crtc_state, &wm_params, wm->wm); wm 5000 drivers/gpu/drm/i915/intel_pm.c skl_compute_transition_wm(crtc_state, &wm_params, wm); wm 5009 drivers/gpu/drm/i915/intel_pm.c struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id]; wm 5013 drivers/gpu/drm/i915/intel_pm.c wm->is_planar = true; wm 5021 drivers/gpu/drm/i915/intel_pm.c skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm); wm 5092 drivers/gpu/drm/i915/intel_pm.c struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; wm 5154 drivers/gpu/drm/i915/intel_pm.c const struct skl_plane_wm *wm = wm 5155 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; wm 5157 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_y[plane_id]; wm 5159 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_uv[plane_id]; wm 5163 drivers/gpu/drm/i915/intel_pm.c &wm->wm[level]); wm 5166 drivers/gpu/drm/i915/intel_pm.c &wm->trans_wm); wm 5174 drivers/gpu/drm/i915/intel_pm.c if (wm->is_planar) wm 5190 drivers/gpu/drm/i915/intel_pm.c const struct skl_plane_wm *wm = wm 5191 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.optimal.planes[plane_id]; wm 5193 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.skl.plane_ddb_y[plane_id]; wm 5197 drivers/gpu/drm/i915/intel_pm.c &wm->wm[level]); wm 5199 drivers/gpu/drm/i915/intel_pm.c skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); wm 5220 drivers/gpu/drm/i915/intel_pm.c if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]) || wm 5292 drivers/gpu/drm/i915/intel_pm.c if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id], wm 5293 drivers/gpu/drm/i915/intel_pm.c &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) && wm 5294 drivers/gpu/drm/i915/intel_pm.c skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id], wm 5295 drivers/gpu/drm/i915/intel_pm.c &new_crtc_state->wm.skl.plane_ddb_uv[plane_id])) wm 5318 drivers/gpu/drm/i915/intel_pm.c memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb)); wm 5357 drivers/gpu/drm/i915/intel_pm.c old_pipe_wm = &old_crtc_state->wm.skl.optimal; wm 5358 drivers/gpu/drm/i915/intel_pm.c new_pipe_wm = &new_crtc_state->wm.skl.optimal; wm 5364 drivers/gpu/drm/i915/intel_pm.c old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id]; wm 5365 drivers/gpu/drm/i915/intel_pm.c new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id]; wm 5389 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en), wm 5390 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en), wm 5391 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en), wm 5392 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en), wm 5394 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en), wm 5395 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en), wm 5396 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en), wm 5397 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en), wm 5403 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l, wm 5404 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l, wm 5405 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l, wm 5406 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l, wm 5407 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l, wm 5408 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l, wm 5409 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l, wm 5410 drivers/gpu/drm/i915/intel_pm.c enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l, wm 5413 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l, wm 5414 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l, wm 5415 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l, wm 5416 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l, wm 5417 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l, wm 5418 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l, wm 5419 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l, wm 5420 drivers/gpu/drm/i915/intel_pm.c enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l, wm 5426 drivers/gpu/drm/i915/intel_pm.c old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b, wm 5427 drivers/gpu/drm/i915/intel_pm.c old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b, wm 5428 drivers/gpu/drm/i915/intel_pm.c old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b, wm 5429 drivers/gpu/drm/i915/intel_pm.c old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b, wm 5431 drivers/gpu/drm/i915/intel_pm.c new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b, wm 5432 drivers/gpu/drm/i915/intel_pm.c new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b, wm 5433 drivers/gpu/drm/i915/intel_pm.c new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b, wm 5434 drivers/gpu/drm/i915/intel_pm.c new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b, wm 5440 drivers/gpu/drm/i915/intel_pm.c old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc, wm 5441 drivers/gpu/drm/i915/intel_pm.c old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc, wm 5442 drivers/gpu/drm/i915/intel_pm.c old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc, wm 5443 drivers/gpu/drm/i915/intel_pm.c old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc, wm 5445 drivers/gpu/drm/i915/intel_pm.c new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc, wm 5446 drivers/gpu/drm/i915/intel_pm.c new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc, wm 5447 drivers/gpu/drm/i915/intel_pm.c new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc, wm 5448 drivers/gpu/drm/i915/intel_pm.c new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc, wm 5468 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->wm.distrust_bios_wm) wm 5491 drivers/gpu/drm/i915/intel_pm.c if (dev_priv->wm.distrust_bios_wm) { wm 5586 drivers/gpu/drm/i915/intel_pm.c &old_crtc_state->wm.skl.optimal.planes[plane_id], wm 5587 drivers/gpu/drm/i915/intel_pm.c &new_crtc_state->wm.skl.optimal.planes[plane_id])) wm 5634 drivers/gpu/drm/i915/intel_pm.c &old_crtc_state->wm.skl.optimal, wm 5635 drivers/gpu/drm/i915/intel_pm.c &new_crtc_state->wm.skl.optimal)) wm 5653 drivers/gpu/drm/i915/intel_pm.c struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal; wm 5673 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 5678 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 5688 drivers/gpu/drm/i915/intel_pm.c const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; wm 5690 drivers/gpu/drm/i915/intel_pm.c if (!wm->pipe_enabled) wm 5693 drivers/gpu/drm/i915/intel_pm.c config->sprites_enabled |= wm->sprites_enabled; wm 5694 drivers/gpu/drm/i915/intel_pm.c config->sprites_scaled |= wm->sprites_scaled; wm 5737 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 5738 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate; wm 5740 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 5749 drivers/gpu/drm/i915/intel_pm.c if (!crtc_state->wm.need_postvbl_update) wm 5752 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 5753 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.ilk = crtc_state->wm.ilk.optimal; wm 5755 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 5780 drivers/gpu/drm/i915/intel_pm.c struct skl_plane_wm *wm = &out->planes[plane_id]; wm 5788 drivers/gpu/drm/i915/intel_pm.c skl_wm_level_from_reg_val(val, &wm->wm[level]); wm 5796 drivers/gpu/drm/i915/intel_pm.c skl_wm_level_from_reg_val(val, &wm->trans_wm); wm 5807 drivers/gpu/drm/i915/intel_pm.c struct skl_ddb_values *hw = &dev_priv->wm.skl_hw; wm 5808 drivers/gpu/drm/i915/intel_pm.c struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; wm 5816 drivers/gpu/drm/i915/intel_pm.c skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal); wm 5824 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.distrust_bios_wm = true; wm 5832 drivers/gpu/drm/i915/intel_pm.c struct ilk_wm_values *hw = &dev_priv->wm.hw; wm 5834 drivers/gpu/drm/i915/intel_pm.c struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal; wm 5859 drivers/gpu/drm/i915/intel_pm.c active->wm[0].enable = true; wm 5860 drivers/gpu/drm/i915/intel_pm.c active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; wm 5861 drivers/gpu/drm/i915/intel_pm.c active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; wm 5862 drivers/gpu/drm/i915/intel_pm.c active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; wm 5873 drivers/gpu/drm/i915/intel_pm.c active->wm[level].enable = true; wm 5876 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.ilk = *active; wm 5885 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_values *wm) wm 5890 drivers/gpu/drm/i915/intel_pm.c wm->sr.plane = _FW_WM(tmp, SR); wm 5891 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); wm 5892 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); wm 5893 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); wm 5896 drivers/gpu/drm/i915/intel_pm.c wm->fbc_en = tmp & DSPFW_FBC_SR_EN; wm 5897 drivers/gpu/drm/i915/intel_pm.c wm->sr.fbc = _FW_WM(tmp, FBC_SR); wm 5898 drivers/gpu/drm/i915/intel_pm.c wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR); wm 5899 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB); wm 5900 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); wm 5901 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); wm 5904 drivers/gpu/drm/i915/intel_pm.c wm->hpll_en = tmp & DSPFW_HPLL_SR_EN; wm 5905 drivers/gpu/drm/i915/intel_pm.c wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); wm 5906 drivers/gpu/drm/i915/intel_pm.c wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR); wm 5907 drivers/gpu/drm/i915/intel_pm.c wm->hpll.plane = _FW_WM(tmp, HPLL_SR); wm 5911 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_values *wm) wm 5919 drivers/gpu/drm/i915/intel_pm.c wm->ddl[pipe].plane[PLANE_PRIMARY] = wm 5921 drivers/gpu/drm/i915/intel_pm.c wm->ddl[pipe].plane[PLANE_CURSOR] = wm 5923 drivers/gpu/drm/i915/intel_pm.c wm->ddl[pipe].plane[PLANE_SPRITE0] = wm 5925 drivers/gpu/drm/i915/intel_pm.c wm->ddl[pipe].plane[PLANE_SPRITE1] = wm 5930 drivers/gpu/drm/i915/intel_pm.c wm->sr.plane = _FW_WM(tmp, SR); wm 5931 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); wm 5932 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); wm 5933 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); wm 5936 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); wm 5937 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); wm 5938 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); wm 5941 drivers/gpu/drm/i915/intel_pm.c wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); wm 5945 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); wm 5946 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); wm 5949 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF); wm 5950 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE); wm 5953 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC); wm 5954 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC); wm 5957 drivers/gpu/drm/i915/intel_pm.c wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; wm 5958 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8; wm 5959 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8; wm 5960 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8; wm 5961 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; wm 5962 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; wm 5963 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; wm 5964 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; wm 5965 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; wm 5966 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; wm 5969 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); wm 5970 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); wm 5973 drivers/gpu/drm/i915/intel_pm.c wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; wm 5974 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; wm 5975 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; wm 5976 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; wm 5977 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; wm 5978 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; wm 5979 drivers/gpu/drm/i915/intel_pm.c wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; wm 5988 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_values *wm = &dev_priv->wm.g4x; wm 5991 drivers/gpu/drm/i915/intel_pm.c g4x_read_wm_values(dev_priv, wm); wm 5993 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; wm 5998 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_state *active = &crtc->wm.active.g4x; wm 6004 drivers/gpu/drm/i915/intel_pm.c active->cxsr = wm->cxsr; wm 6005 drivers/gpu/drm/i915/intel_pm.c active->hpll_en = wm->hpll_en; wm 6006 drivers/gpu/drm/i915/intel_pm.c active->fbc_en = wm->fbc_en; wm 6008 drivers/gpu/drm/i915/intel_pm.c active->sr = wm->sr; wm 6009 drivers/gpu/drm/i915/intel_pm.c active->hpll = wm->hpll; wm 6012 drivers/gpu/drm/i915/intel_pm.c active->wm.plane[plane_id] = wm 6013 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe].plane[plane_id]; wm 6016 drivers/gpu/drm/i915/intel_pm.c if (wm->cxsr && wm->hpll_en) wm 6018 drivers/gpu/drm/i915/intel_pm.c else if (wm->cxsr) wm 6024 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; wm 6026 drivers/gpu/drm/i915/intel_pm.c raw->plane[plane_id] = active->wm.plane[plane_id]; wm 6031 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; wm 6040 drivers/gpu/drm/i915/intel_pm.c raw = &crtc_state->wm.g4x.raw[level]; wm 6052 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.optimal = *active; wm 6053 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.intermediate = *active; wm 6057 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe].plane[PLANE_PRIMARY], wm 6058 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe].plane[PLANE_CURSOR], wm 6059 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe].plane[PLANE_SPRITE0]); wm 6063 drivers/gpu/drm/i915/intel_pm.c wm->sr.plane, wm->sr.cursor, wm->sr.fbc); wm 6065 drivers/gpu/drm/i915/intel_pm.c wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc); wm 6067 drivers/gpu/drm/i915/intel_pm.c yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en)); wm 6075 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 6084 drivers/gpu/drm/i915/intel_pm.c struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; wm 6093 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.g4x.raw[level]; wm 6096 drivers/gpu/drm/i915/intel_pm.c wm_state->wm.plane[plane_id] = 0; wm 6102 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.g4x.raw[level]; wm 6116 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.intermediate = wm 6117 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.g4x.optimal; wm 6118 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; wm 6123 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 6128 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_values *wm = &dev_priv->wm.vlv; wm 6132 drivers/gpu/drm/i915/intel_pm.c vlv_read_wm_values(dev_priv, wm); wm 6134 drivers/gpu/drm/i915/intel_pm.c wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; wm 6135 drivers/gpu/drm/i915/intel_pm.c wm->level = VLV_WM_LEVEL_PM2; wm 6142 drivers/gpu/drm/i915/intel_pm.c wm->level = VLV_WM_LEVEL_PM5; wm 6161 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; wm 6165 drivers/gpu/drm/i915/intel_pm.c wm->level = VLV_WM_LEVEL_DDR_DVFS; wm 6174 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_state *active = &crtc->wm.active.vlv; wm 6176 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; wm 6183 drivers/gpu/drm/i915/intel_pm.c active->num_levels = wm->level + 1; wm 6184 drivers/gpu/drm/i915/intel_pm.c active->cxsr = wm->cxsr; wm 6188 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.raw[level]; wm 6190 drivers/gpu/drm/i915/intel_pm.c active->sr[level].plane = wm->sr.plane; wm 6191 drivers/gpu/drm/i915/intel_pm.c active->sr[level].cursor = wm->sr.cursor; wm 6194 drivers/gpu/drm/i915/intel_pm.c active->wm[level].plane[plane_id] = wm 6195 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe].plane[plane_id]; wm 6198 drivers/gpu/drm/i915/intel_pm.c vlv_invert_wm_value(active->wm[level].plane[plane_id], wm 6208 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.optimal = *active; wm 6209 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.intermediate = *active; wm 6213 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe].plane[PLANE_PRIMARY], wm 6214 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe].plane[PLANE_CURSOR], wm 6215 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe].plane[PLANE_SPRITE0], wm 6216 drivers/gpu/drm/i915/intel_pm.c wm->pipe[pipe].plane[PLANE_SPRITE1]); wm 6220 drivers/gpu/drm/i915/intel_pm.c wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); wm 6228 drivers/gpu/drm/i915/intel_pm.c mutex_lock(&dev_priv->wm.wm_mutex); wm 6237 drivers/gpu/drm/i915/intel_pm.c struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; wm 6239 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.fifo_state; wm 6248 drivers/gpu/drm/i915/intel_pm.c &crtc_state->wm.vlv.raw[level]; wm 6252 drivers/gpu/drm/i915/intel_pm.c wm_state->wm[level].plane[plane_id] = wm 6262 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.intermediate = wm 6263 drivers/gpu/drm/i915/intel_pm.c crtc_state->wm.vlv.optimal; wm 6264 drivers/gpu/drm/i915/intel_pm.c crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; wm 6269 drivers/gpu/drm/i915/intel_pm.c mutex_unlock(&dev_priv->wm.wm_mutex); wm 6290 drivers/gpu/drm/i915/intel_pm.c struct ilk_wm_values *hw = &dev_priv->wm.hw; wm 9795 drivers/gpu/drm/i915/intel_pm.c if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] && wm 9796 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || wm 9797 drivers/gpu/drm/i915/intel_pm.c (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] && wm 9798 drivers/gpu/drm/i915/intel_pm.c dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { wm 8944 drivers/gpu/drm/radeon/cik.c static u32 dce8_dram_bandwidth(struct dce8_wm_params *wm) wm 8952 drivers/gpu/drm/radeon/cik.c yclk.full = dfixed_const(wm->yclk); wm 8954 drivers/gpu/drm/radeon/cik.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 8973 drivers/gpu/drm/radeon/cik.c static u32 dce8_dram_bandwidth_for_display(struct dce8_wm_params *wm) wm 8981 drivers/gpu/drm/radeon/cik.c yclk.full = dfixed_const(wm->yclk); wm 8983 drivers/gpu/drm/radeon/cik.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 9002 drivers/gpu/drm/radeon/cik.c static u32 dce8_data_return_bandwidth(struct dce8_wm_params *wm) wm 9010 drivers/gpu/drm/radeon/cik.c sclk.full = dfixed_const(wm->sclk); wm 9031 drivers/gpu/drm/radeon/cik.c static u32 dce8_dmif_request_bandwidth(struct dce8_wm_params *wm) wm 9039 drivers/gpu/drm/radeon/cik.c disp_clk.full = dfixed_const(wm->disp_clk); wm 9062 drivers/gpu/drm/radeon/cik.c static u32 dce8_available_bandwidth(struct dce8_wm_params *wm) wm 9065 drivers/gpu/drm/radeon/cik.c u32 dram_bandwidth = dce8_dram_bandwidth(wm); wm 9066 drivers/gpu/drm/radeon/cik.c u32 data_return_bandwidth = dce8_data_return_bandwidth(wm); wm 9067 drivers/gpu/drm/radeon/cik.c u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm); wm 9081 drivers/gpu/drm/radeon/cik.c static u32 dce8_average_bandwidth(struct dce8_wm_params *wm) wm 9094 drivers/gpu/drm/radeon/cik.c line_time.full = dfixed_const(wm->active_time + wm->blank_time); wm 9096 drivers/gpu/drm/radeon/cik.c bpp.full = dfixed_const(wm->bytes_per_pixel); wm 9097 drivers/gpu/drm/radeon/cik.c src_width.full = dfixed_const(wm->src_width); wm 9099 drivers/gpu/drm/radeon/cik.c bandwidth.full = dfixed_mul(bandwidth, wm->vsc); wm 9114 drivers/gpu/drm/radeon/cik.c static u32 dce8_latency_watermark(struct dce8_wm_params *wm) wm 9118 drivers/gpu/drm/radeon/cik.c u32 available_bandwidth = dce8_available_bandwidth(wm); wm 9121 drivers/gpu/drm/radeon/cik.c u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ wm 9122 drivers/gpu/drm/radeon/cik.c u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + wm 9123 drivers/gpu/drm/radeon/cik.c (wm->num_heads * cursor_line_pair_return_time); wm 9129 drivers/gpu/drm/radeon/cik.c if (wm->num_heads == 0) wm 9134 drivers/gpu/drm/radeon/cik.c if ((wm->vsc.full > a.full) || wm 9135 drivers/gpu/drm/radeon/cik.c ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || wm 9136 drivers/gpu/drm/radeon/cik.c (wm->vtaps >= 5) || wm 9137 drivers/gpu/drm/radeon/cik.c ((wm->vsc.full >= a.full) && wm->interlaced)) wm 9143 drivers/gpu/drm/radeon/cik.c b.full = dfixed_const(wm->num_heads); wm 9145 drivers/gpu/drm/radeon/cik.c tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); wm 9148 drivers/gpu/drm/radeon/cik.c lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); wm 9150 drivers/gpu/drm/radeon/cik.c a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); wm 9157 drivers/gpu/drm/radeon/cik.c if (line_fill_time < wm->active_time) wm 9160 drivers/gpu/drm/radeon/cik.c return latency + (line_fill_time - wm->active_time); wm 9175 drivers/gpu/drm/radeon/cik.c static bool dce8_average_bandwidth_vs_dram_bandwidth_for_display(struct dce8_wm_params *wm) wm 9177 drivers/gpu/drm/radeon/cik.c if (dce8_average_bandwidth(wm) <= wm 9178 drivers/gpu/drm/radeon/cik.c (dce8_dram_bandwidth_for_display(wm) / wm->num_heads)) wm 9195 drivers/gpu/drm/radeon/cik.c static bool dce8_average_bandwidth_vs_available_bandwidth(struct dce8_wm_params *wm) wm 9197 drivers/gpu/drm/radeon/cik.c if (dce8_average_bandwidth(wm) <= wm 9198 drivers/gpu/drm/radeon/cik.c (dce8_available_bandwidth(wm) / wm->num_heads)) wm 9213 drivers/gpu/drm/radeon/cik.c static bool dce8_check_latency_hiding(struct dce8_wm_params *wm) wm 9215 drivers/gpu/drm/radeon/cik.c u32 lb_partitions = wm->lb_size / wm->src_width; wm 9216 drivers/gpu/drm/radeon/cik.c u32 line_time = wm->active_time + wm->blank_time; wm 9222 drivers/gpu/drm/radeon/cik.c if (wm->vsc.full > a.full) wm 9225 drivers/gpu/drm/radeon/cik.c if (lb_partitions <= (wm->vtaps + 1)) wm 9231 drivers/gpu/drm/radeon/cik.c latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); wm 9233 drivers/gpu/drm/radeon/cik.c if (dce8_latency_watermark(wm) <= latency_hiding) wm 1947 drivers/gpu/drm/radeon/evergreen.c static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm) wm 1955 drivers/gpu/drm/radeon/evergreen.c yclk.full = dfixed_const(wm->yclk); wm 1957 drivers/gpu/drm/radeon/evergreen.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 1967 drivers/gpu/drm/radeon/evergreen.c static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm) wm 1975 drivers/gpu/drm/radeon/evergreen.c yclk.full = dfixed_const(wm->yclk); wm 1977 drivers/gpu/drm/radeon/evergreen.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 1987 drivers/gpu/drm/radeon/evergreen.c static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm) wm 1995 drivers/gpu/drm/radeon/evergreen.c sclk.full = dfixed_const(wm->sclk); wm 2007 drivers/gpu/drm/radeon/evergreen.c static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm) wm 2015 drivers/gpu/drm/radeon/evergreen.c disp_clk.full = dfixed_const(wm->disp_clk); wm 2027 drivers/gpu/drm/radeon/evergreen.c static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm) wm 2030 drivers/gpu/drm/radeon/evergreen.c u32 dram_bandwidth = evergreen_dram_bandwidth(wm); wm 2031 drivers/gpu/drm/radeon/evergreen.c u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm); wm 2032 drivers/gpu/drm/radeon/evergreen.c u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm); wm 2037 drivers/gpu/drm/radeon/evergreen.c static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm) wm 2050 drivers/gpu/drm/radeon/evergreen.c line_time.full = dfixed_const(wm->active_time + wm->blank_time); wm 2052 drivers/gpu/drm/radeon/evergreen.c bpp.full = dfixed_const(wm->bytes_per_pixel); wm 2053 drivers/gpu/drm/radeon/evergreen.c src_width.full = dfixed_const(wm->src_width); wm 2055 drivers/gpu/drm/radeon/evergreen.c bandwidth.full = dfixed_mul(bandwidth, wm->vsc); wm 2061 drivers/gpu/drm/radeon/evergreen.c static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm) wm 2065 drivers/gpu/drm/radeon/evergreen.c u32 available_bandwidth = evergreen_available_bandwidth(wm); wm 2068 drivers/gpu/drm/radeon/evergreen.c u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ wm 2069 drivers/gpu/drm/radeon/evergreen.c u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + wm 2070 drivers/gpu/drm/radeon/evergreen.c (wm->num_heads * cursor_line_pair_return_time); wm 2075 drivers/gpu/drm/radeon/evergreen.c if (wm->num_heads == 0) wm 2080 drivers/gpu/drm/radeon/evergreen.c if ((wm->vsc.full > a.full) || wm 2081 drivers/gpu/drm/radeon/evergreen.c ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || wm 2082 drivers/gpu/drm/radeon/evergreen.c (wm->vtaps >= 5) || wm 2083 drivers/gpu/drm/radeon/evergreen.c ((wm->vsc.full >= a.full) && wm->interlaced)) wm 2089 drivers/gpu/drm/radeon/evergreen.c b.full = dfixed_const(wm->num_heads); wm 2092 drivers/gpu/drm/radeon/evergreen.c lb_fill_bw = min(dfixed_trunc(a), wm->disp_clk * wm->bytes_per_pixel / 1000); wm 2094 drivers/gpu/drm/radeon/evergreen.c a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); wm 2101 drivers/gpu/drm/radeon/evergreen.c if (line_fill_time < wm->active_time) wm 2104 drivers/gpu/drm/radeon/evergreen.c return latency + (line_fill_time - wm->active_time); wm 2108 drivers/gpu/drm/radeon/evergreen.c static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm) wm 2110 drivers/gpu/drm/radeon/evergreen.c if (evergreen_average_bandwidth(wm) <= wm 2111 drivers/gpu/drm/radeon/evergreen.c (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads)) wm 2117 drivers/gpu/drm/radeon/evergreen.c static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm) wm 2119 drivers/gpu/drm/radeon/evergreen.c if (evergreen_average_bandwidth(wm) <= wm 2120 drivers/gpu/drm/radeon/evergreen.c (evergreen_available_bandwidth(wm) / wm->num_heads)) wm 2126 drivers/gpu/drm/radeon/evergreen.c static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm) wm 2128 drivers/gpu/drm/radeon/evergreen.c u32 lb_partitions = wm->lb_size / wm->src_width; wm 2129 drivers/gpu/drm/radeon/evergreen.c u32 line_time = wm->active_time + wm->blank_time; wm 2135 drivers/gpu/drm/radeon/evergreen.c if (wm->vsc.full > a.full) wm 2138 drivers/gpu/drm/radeon/evergreen.c if (lb_partitions <= (wm->vtaps + 1)) wm 2144 drivers/gpu/drm/radeon/evergreen.c latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); wm 2146 drivers/gpu/drm/radeon/evergreen.c if (evergreen_latency_watermark(wm) <= latency_hiding) wm 274 drivers/gpu/drm/radeon/rs690.c struct rs690_watermark *wm, wm 286 drivers/gpu/drm/radeon/rs690.c wm->lb_request_fifo_depth = 4; wm 306 drivers/gpu/drm/radeon/rs690.c wm->num_line_pair.full = dfixed_const(2); wm 308 drivers/gpu/drm/radeon/rs690.c wm->num_line_pair.full = dfixed_const(1); wm 313 drivers/gpu/drm/radeon/rs690.c request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); wm 316 drivers/gpu/drm/radeon/rs690.c wm->lb_request_fifo_depth = 4; wm 318 drivers/gpu/drm/radeon/rs690.c wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); wm 343 drivers/gpu/drm/radeon/rs690.c wm->consumption_rate.full = dfixed_div(a, consumption_time); wm 361 drivers/gpu/drm/radeon/rs690.c wm->active_time.full = dfixed_mul(line_time, b); wm 362 drivers/gpu/drm/radeon/rs690.c wm->active_time.full = dfixed_div(wm->active_time, a); wm 408 drivers/gpu/drm/radeon/rs690.c if (dfixed_trunc(wm->num_line_pair) > 1) { wm 410 drivers/gpu/drm/radeon/rs690.c wm->worst_case_latency.full = dfixed_mul(a, chunk_time); wm 411 drivers/gpu/drm/radeon/rs690.c wm->worst_case_latency.full += read_delay_latency.full; wm 414 drivers/gpu/drm/radeon/rs690.c wm->worst_case_latency.full = dfixed_mul(a, chunk_time); wm 415 drivers/gpu/drm/radeon/rs690.c wm->worst_case_latency.full += read_delay_latency.full; wm 428 drivers/gpu/drm/radeon/rs690.c if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { wm 431 drivers/gpu/drm/radeon/rs690.c tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); wm 437 drivers/gpu/drm/radeon/rs690.c wm->dbpp.full = dfixed_const(4 * 8); wm 443 drivers/gpu/drm/radeon/rs690.c wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); wm 444 drivers/gpu/drm/radeon/rs690.c wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); wm 445 drivers/gpu/drm/radeon/rs690.c wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); wm 448 drivers/gpu/drm/radeon/rs690.c estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; wm 451 drivers/gpu/drm/radeon/rs690.c wm->priority_mark.full = dfixed_const(10); wm 454 drivers/gpu/drm/radeon/rs690.c wm->priority_mark.full = dfixed_div(estimated_width, a); wm 455 drivers/gpu/drm/radeon/rs690.c wm->priority_mark.full = dfixed_ceil(wm->priority_mark); wm 456 drivers/gpu/drm/radeon/rs690.c wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; wm 957 drivers/gpu/drm/radeon/rv515.c struct rv515_watermark *wm, wm 969 drivers/gpu/drm/radeon/rv515.c wm->lb_request_fifo_depth = 4; wm 986 drivers/gpu/drm/radeon/rv515.c wm->num_line_pair.full = dfixed_const(2); wm 988 drivers/gpu/drm/radeon/rv515.c wm->num_line_pair.full = dfixed_const(1); wm 993 drivers/gpu/drm/radeon/rv515.c request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair); wm 996 drivers/gpu/drm/radeon/rv515.c wm->lb_request_fifo_depth = 4; wm 998 drivers/gpu/drm/radeon/rv515.c wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth); wm 1023 drivers/gpu/drm/radeon/rv515.c wm->consumption_rate.full = dfixed_div(a, consumption_time); wm 1041 drivers/gpu/drm/radeon/rv515.c wm->active_time.full = dfixed_mul(line_time, b); wm 1042 drivers/gpu/drm/radeon/rv515.c wm->active_time.full = dfixed_div(wm->active_time, a); wm 1061 drivers/gpu/drm/radeon/rv515.c if (dfixed_trunc(wm->num_line_pair) > 1) { wm 1063 drivers/gpu/drm/radeon/rv515.c wm->worst_case_latency.full = dfixed_mul(a, chunk_time); wm 1064 drivers/gpu/drm/radeon/rv515.c wm->worst_case_latency.full += read_delay_latency.full; wm 1066 drivers/gpu/drm/radeon/rv515.c wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full; wm 1079 drivers/gpu/drm/radeon/rv515.c if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) { wm 1082 drivers/gpu/drm/radeon/rv515.c tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2); wm 1088 drivers/gpu/drm/radeon/rv515.c wm->dbpp.full = dfixed_const(2 * 16); wm 1094 drivers/gpu/drm/radeon/rv515.c wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay); wm 1095 drivers/gpu/drm/radeon/rv515.c wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a); wm 1096 drivers/gpu/drm/radeon/rv515.c wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max); wm 1099 drivers/gpu/drm/radeon/rv515.c estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full; wm 1102 drivers/gpu/drm/radeon/rv515.c wm->priority_mark.full = wm->priority_mark_max.full; wm 1105 drivers/gpu/drm/radeon/rv515.c wm->priority_mark.full = dfixed_div(estimated_width, a); wm 1106 drivers/gpu/drm/radeon/rv515.c wm->priority_mark.full = dfixed_ceil(wm->priority_mark); wm 1107 drivers/gpu/drm/radeon/rv515.c wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full; wm 2073 drivers/gpu/drm/radeon/si.c static u32 dce6_dram_bandwidth(struct dce6_wm_params *wm) wm 2081 drivers/gpu/drm/radeon/si.c yclk.full = dfixed_const(wm->yclk); wm 2083 drivers/gpu/drm/radeon/si.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 2093 drivers/gpu/drm/radeon/si.c static u32 dce6_dram_bandwidth_for_display(struct dce6_wm_params *wm) wm 2101 drivers/gpu/drm/radeon/si.c yclk.full = dfixed_const(wm->yclk); wm 2103 drivers/gpu/drm/radeon/si.c dram_channels.full = dfixed_const(wm->dram_channels * 4); wm 2113 drivers/gpu/drm/radeon/si.c static u32 dce6_data_return_bandwidth(struct dce6_wm_params *wm) wm 2121 drivers/gpu/drm/radeon/si.c sclk.full = dfixed_const(wm->sclk); wm 2133 drivers/gpu/drm/radeon/si.c static u32 dce6_get_dmif_bytes_per_request(struct dce6_wm_params *wm) wm 2138 drivers/gpu/drm/radeon/si.c static u32 dce6_dmif_request_bandwidth(struct dce6_wm_params *wm) wm 2147 drivers/gpu/drm/radeon/si.c disp_clk.full = dfixed_const(wm->disp_clk); wm 2149 drivers/gpu/drm/radeon/si.c a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm) / 2); wm 2153 drivers/gpu/drm/radeon/si.c sclk.full = dfixed_const(wm->sclk); wm 2155 drivers/gpu/drm/radeon/si.c a.full = dfixed_const(dce6_get_dmif_bytes_per_request(wm)); wm 2170 drivers/gpu/drm/radeon/si.c static u32 dce6_available_bandwidth(struct dce6_wm_params *wm) wm 2173 drivers/gpu/drm/radeon/si.c u32 dram_bandwidth = dce6_dram_bandwidth(wm); wm 2174 drivers/gpu/drm/radeon/si.c u32 data_return_bandwidth = dce6_data_return_bandwidth(wm); wm 2175 drivers/gpu/drm/radeon/si.c u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm); wm 2180 drivers/gpu/drm/radeon/si.c static u32 dce6_average_bandwidth(struct dce6_wm_params *wm) wm 2193 drivers/gpu/drm/radeon/si.c line_time.full = dfixed_const(wm->active_time + wm->blank_time); wm 2195 drivers/gpu/drm/radeon/si.c bpp.full = dfixed_const(wm->bytes_per_pixel); wm 2196 drivers/gpu/drm/radeon/si.c src_width.full = dfixed_const(wm->src_width); wm 2198 drivers/gpu/drm/radeon/si.c bandwidth.full = dfixed_mul(bandwidth, wm->vsc); wm 2204 drivers/gpu/drm/radeon/si.c static u32 dce6_latency_watermark(struct dce6_wm_params *wm) wm 2208 drivers/gpu/drm/radeon/si.c u32 available_bandwidth = dce6_available_bandwidth(wm); wm 2211 drivers/gpu/drm/radeon/si.c u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */ wm 2212 drivers/gpu/drm/radeon/si.c u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) + wm 2213 drivers/gpu/drm/radeon/si.c (wm->num_heads * cursor_line_pair_return_time); wm 2219 drivers/gpu/drm/radeon/si.c if (wm->num_heads == 0) wm 2224 drivers/gpu/drm/radeon/si.c if ((wm->vsc.full > a.full) || wm 2225 drivers/gpu/drm/radeon/si.c ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) || wm 2226 drivers/gpu/drm/radeon/si.c (wm->vtaps >= 5) || wm 2227 drivers/gpu/drm/radeon/si.c ((wm->vsc.full >= a.full) && wm->interlaced)) wm 2233 drivers/gpu/drm/radeon/si.c b.full = dfixed_const(wm->num_heads); wm 2235 drivers/gpu/drm/radeon/si.c tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512); wm 2238 drivers/gpu/drm/radeon/si.c lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000); wm 2240 drivers/gpu/drm/radeon/si.c a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel); wm 2247 drivers/gpu/drm/radeon/si.c if (line_fill_time < wm->active_time) wm 2250 drivers/gpu/drm/radeon/si.c return latency + (line_fill_time - wm->active_time); wm 2254 drivers/gpu/drm/radeon/si.c static bool dce6_average_bandwidth_vs_dram_bandwidth_for_display(struct dce6_wm_params *wm) wm 2256 drivers/gpu/drm/radeon/si.c if (dce6_average_bandwidth(wm) <= wm 2257 drivers/gpu/drm/radeon/si.c (dce6_dram_bandwidth_for_display(wm) / wm->num_heads)) wm 2263 drivers/gpu/drm/radeon/si.c static bool dce6_average_bandwidth_vs_available_bandwidth(struct dce6_wm_params *wm) wm 2265 drivers/gpu/drm/radeon/si.c if (dce6_average_bandwidth(wm) <= wm 2266 drivers/gpu/drm/radeon/si.c (dce6_available_bandwidth(wm) / wm->num_heads)) wm 2272 drivers/gpu/drm/radeon/si.c static bool dce6_check_latency_hiding(struct dce6_wm_params *wm) wm 2274 drivers/gpu/drm/radeon/si.c u32 lb_partitions = wm->lb_size / wm->src_width; wm 2275 drivers/gpu/drm/radeon/si.c u32 line_time = wm->active_time + wm->blank_time; wm 2281 drivers/gpu/drm/radeon/si.c if (wm->vsc.full > a.full) wm 2284 drivers/gpu/drm/radeon/si.c if (lb_partitions <= (wm->vtaps + 1)) wm 2290 drivers/gpu/drm/radeon/si.c latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time); wm 2292 drivers/gpu/drm/radeon/si.c if (dce6_latency_watermark(wm) <= latency_hiding) wm 680 drivers/gpu/drm/radeon/trinity_dpm.c u32 index, u32 wm) wm 687 drivers/gpu/drm/radeon/trinity_dpm.c value |= DISPLAY_WM(wm); wm 692 drivers/gpu/drm/radeon/trinity_dpm.c u32 index, u32 wm) wm 699 drivers/gpu/drm/radeon/trinity_dpm.c value |= VCE_WM(wm); wm 768 drivers/iio/accel/bmc150-accel-core.c int wm; wm 771 drivers/iio/accel/bmc150-accel-core.c wm = data->watermark; wm 774 drivers/iio/accel/bmc150-accel-core.c return sprintf(buf, "%d\n", wm); wm 101 drivers/input/touchscreen/mainstone-wm97xx.c static void wm97xx_acc_pen_up(struct wm97xx *wm) wm 109 drivers/input/touchscreen/mainstone-wm97xx.c static void wm97xx_acc_pen_up(struct wm97xx *wm) wm 120 drivers/input/touchscreen/mainstone-wm97xx.c static int wm97xx_acc_pen_down(struct wm97xx *wm) wm 150 drivers/input/touchscreen/mainstone-wm97xx.c dev_dbg(wm->dev, "Raw coordinates: x=%x, y=%x, p=%x\n", wm 161 drivers/input/touchscreen/mainstone-wm97xx.c input_report_abs(wm->input_dev, ABS_X, x & 0xfff); wm 162 drivers/input/touchscreen/mainstone-wm97xx.c input_report_abs(wm->input_dev, ABS_Y, y & 0xfff); wm 163 drivers/input/touchscreen/mainstone-wm97xx.c input_report_abs(wm->input_dev, ABS_PRESSURE, p & 0xfff); wm 164 drivers/input/touchscreen/mainstone-wm97xx.c input_report_key(wm->input_dev, BTN_TOUCH, (p != 0)); wm 165 drivers/input/touchscreen/mainstone-wm97xx.c input_sync(wm->input_dev); wm 172 drivers/input/touchscreen/mainstone-wm97xx.c static int wm97xx_acc_startup(struct wm97xx *wm) wm 177 drivers/input/touchscreen/mainstone-wm97xx.c if (wm->ac97 == NULL) wm 182 drivers/input/touchscreen/mainstone-wm97xx.c if (wm->id != cinfo[idx].id) wm 188 drivers/input/touchscreen/mainstone-wm97xx.c wm->acc_rate = cinfo[sp_idx].code; wm 189 drivers/input/touchscreen/mainstone-wm97xx.c wm->acc_slot = ac97_touch_slot; wm 190 drivers/input/touchscreen/mainstone-wm97xx.c dev_info(wm->dev, wm 200 drivers/input/touchscreen/mainstone-wm97xx.c wm->variant = WM97xx_WM1613; wm 215 drivers/input/touchscreen/mainstone-wm97xx.c wm->pen_irq = gpio_to_irq(irq); wm 216 drivers/input/touchscreen/mainstone-wm97xx.c irq_set_irq_type(wm->pen_irq, IRQ_TYPE_EDGE_BOTH); wm 222 drivers/input/touchscreen/mainstone-wm97xx.c switch (wm->id) { wm 228 drivers/input/touchscreen/mainstone-wm97xx.c wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN, wm 232 drivers/input/touchscreen/mainstone-wm97xx.c wm97xx_config_gpio(wm, WM97XX_GPIO_2, WM97XX_GPIO_OUT, wm 238 drivers/input/touchscreen/mainstone-wm97xx.c dev_err(wm->dev, wm 249 drivers/input/touchscreen/mainstone-wm97xx.c static void wm97xx_acc_shutdown(struct wm97xx *wm) wm 255 drivers/input/touchscreen/mainstone-wm97xx.c wm->pen_irq = 0; wm 259 drivers/input/touchscreen/mainstone-wm97xx.c static void wm97xx_irq_enable(struct wm97xx *wm, int enable) wm 262 drivers/input/touchscreen/mainstone-wm97xx.c enable_irq(wm->pen_irq); wm 264 drivers/input/touchscreen/mainstone-wm97xx.c disable_irq_nosync(wm->pen_irq); wm 279 drivers/input/touchscreen/mainstone-wm97xx.c struct wm97xx *wm = platform_get_drvdata(pdev); wm 281 drivers/input/touchscreen/mainstone-wm97xx.c return wm97xx_register_mach_ops(wm, &mainstone_mach_ops); wm 286 drivers/input/touchscreen/mainstone-wm97xx.c struct wm97xx *wm = platform_get_drvdata(pdev); wm 288 drivers/input/touchscreen/mainstone-wm97xx.c wm97xx_unregister_mach_ops(wm); wm 133 drivers/input/touchscreen/wm9705.c static void wm9705_phy_init(struct wm97xx *wm) wm 141 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_AUX, 0x8000); wm 142 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_VIDEO, 0x8000); wm 147 drivers/input/touchscreen/wm9705.c dev_dbg(wm->dev, wm 150 drivers/input/touchscreen/wm9705.c dev_dbg(wm->dev, wm 158 drivers/input/touchscreen/wm9705.c dev_dbg(wm->dev, "supplied delay out of range."); wm 164 drivers/input/touchscreen/wm9705.c dev_dbg(wm->dev, "setting adc sample delay to %d u Secs.", wm 169 drivers/input/touchscreen/wm9705.c dev_dbg(wm->dev, "setting pdd to Vmid/%d", 1 - (pdd & 0x000f)); wm 174 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1); wm 175 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2); wm 178 drivers/input/touchscreen/wm9705.c static void wm9705_dig_enable(struct wm97xx *wm, int enable) wm 181 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, wm 182 drivers/input/touchscreen/wm9705.c wm->dig[2] | WM97XX_PRP_DET_DIG); wm 183 drivers/input/touchscreen/wm9705.c wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); /* dummy read */ wm 185 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, wm 186 drivers/input/touchscreen/wm9705.c wm->dig[2] & ~WM97XX_PRP_DET_DIG); wm 189 drivers/input/touchscreen/wm9705.c static void wm9705_aux_prepare(struct wm97xx *wm) wm 191 drivers/input/touchscreen/wm9705.c memcpy(wm->dig_save, wm->dig, sizeof(wm->dig)); wm 192 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, 0); wm 193 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, WM97XX_PRP_DET_DIG); wm 196 drivers/input/touchscreen/wm9705.c static void wm9705_dig_restore(struct wm97xx *wm) wm 198 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, wm->dig_save[1]); wm 199 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, wm->dig_save[2]); wm 202 drivers/input/touchscreen/wm9705.c static inline int is_pden(struct wm97xx *wm) wm 204 drivers/input/touchscreen/wm9705.c return wm->dig[2] & WM9705_PDEN; wm 210 drivers/input/touchscreen/wm9705.c static int wm9705_poll_sample(struct wm97xx *wm, int adcsel, int *sample) wm 215 drivers/input/touchscreen/wm9705.c if (wants_pen && !wm->pen_probably_down) { wm 216 drivers/input/touchscreen/wm9705.c u16 data = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 219 drivers/input/touchscreen/wm9705.c wm->pen_probably_down = 1; wm 223 drivers/input/touchscreen/wm9705.c if (wm->mach_ops && wm->mach_ops->pre_sample) wm 224 drivers/input/touchscreen/wm9705.c wm->mach_ops->pre_sample(adcsel); wm 225 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, (adcsel & WM97XX_ADCSEL_MASK) wm 232 drivers/input/touchscreen/wm9705.c while ((wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER1) & WM97XX_POLL) wm 240 drivers/input/touchscreen/wm9705.c if (is_pden(wm)) wm 241 drivers/input/touchscreen/wm9705.c wm->pen_probably_down = 0; wm 243 drivers/input/touchscreen/wm9705.c dev_dbg(wm->dev, "adc sample timeout"); wm 247 drivers/input/touchscreen/wm9705.c *sample = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 248 drivers/input/touchscreen/wm9705.c if (wm->mach_ops && wm->mach_ops->post_sample) wm 249 drivers/input/touchscreen/wm9705.c wm->mach_ops->post_sample(adcsel); wm 253 drivers/input/touchscreen/wm9705.c dev_dbg(wm->dev, "adc wrong sample, wanted %x got %x", wm 260 drivers/input/touchscreen/wm9705.c wm->pen_probably_down = 0; wm 270 drivers/input/touchscreen/wm9705.c static int wm9705_poll_touch(struct wm97xx *wm, struct wm97xx_data *data) wm 274 drivers/input/touchscreen/wm9705.c rc = wm9705_poll_sample(wm, WM97XX_ADCSEL_X | WM97XX_PEN_DOWN, &data->x); wm 277 drivers/input/touchscreen/wm9705.c rc = wm9705_poll_sample(wm, WM97XX_ADCSEL_Y | WM97XX_PEN_DOWN, &data->y); wm 281 drivers/input/touchscreen/wm9705.c rc = wm9705_poll_sample(wm, WM97XX_ADCSEL_PRES | WM97XX_PEN_DOWN, &data->p); wm 294 drivers/input/touchscreen/wm9705.c static int wm9705_acc_enable(struct wm97xx *wm, int enable) wm 299 drivers/input/touchscreen/wm9705.c dig1 = wm->dig[1]; wm 300 drivers/input/touchscreen/wm9705.c dig2 = wm->dig[2]; wm 304 drivers/input/touchscreen/wm9705.c if (wm->mach_ops->acc_startup && wm 305 drivers/input/touchscreen/wm9705.c (ret = wm->mach_ops->acc_startup(wm)) < 0) wm 311 drivers/input/touchscreen/wm9705.c WM97XX_SLT(wm->acc_slot) | wm 312 drivers/input/touchscreen/wm9705.c WM97XX_RATE(wm->acc_rate); wm 319 drivers/input/touchscreen/wm9705.c if (wm->mach_ops->acc_shutdown) wm 320 drivers/input/touchscreen/wm9705.c wm->mach_ops->acc_shutdown(wm); wm 323 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1); wm 324 drivers/input/touchscreen/wm9705.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2); wm 151 drivers/input/touchscreen/wm9712.c static void wm9712_phy_init(struct wm97xx *wm) wm 160 drivers/input/touchscreen/wm9712.c dev_dbg(wm->dev, "setting pen detect pull-up to %d Ohms\n", wm 167 drivers/input/touchscreen/wm9712.c dev_dbg(wm->dev, "setting 5-wire touchscreen mode.\n"); wm 170 drivers/input/touchscreen/wm9712.c dev_warn(wm->dev, "pressure measurement is not " wm 179 drivers/input/touchscreen/wm9712.c dev_dbg(wm->dev, wm 182 drivers/input/touchscreen/wm9712.c dev_dbg(wm->dev, wm 189 drivers/input/touchscreen/wm9712.c dev_dbg(wm->dev, "supplied delay out of range.\n"); wm 194 drivers/input/touchscreen/wm9712.c dev_dbg(wm->dev, "setting adc sample delay to %d u Secs.\n", wm 202 drivers/input/touchscreen/wm9712.c reg = wm97xx_reg_read(wm, AC97_MISC_AFE); wm 203 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_MISC_AFE, reg | WM97XX_GPIO_4); wm 204 drivers/input/touchscreen/wm9712.c reg = wm97xx_reg_read(wm, AC97_GPIO_CFG); wm 205 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_GPIO_CFG, reg | WM97XX_GPIO_4); wm 212 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1); wm 213 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2); wm 216 drivers/input/touchscreen/wm9712.c static void wm9712_dig_enable(struct wm97xx *wm, int enable) wm 218 drivers/input/touchscreen/wm9712.c u16 dig2 = wm->dig[2]; wm 221 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, wm 223 drivers/input/touchscreen/wm9712.c wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); /* dummy read */ wm 225 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, wm 229 drivers/input/touchscreen/wm9712.c static void wm9712_aux_prepare(struct wm97xx *wm) wm 231 drivers/input/touchscreen/wm9712.c memcpy(wm->dig_save, wm->dig, sizeof(wm->dig)); wm 232 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, 0); wm 233 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, WM97XX_PRP_DET_DIG); wm 236 drivers/input/touchscreen/wm9712.c static void wm9712_dig_restore(struct wm97xx *wm) wm 238 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, wm->dig_save[1]); wm 239 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, wm->dig_save[2]); wm 242 drivers/input/touchscreen/wm9712.c static inline int is_pden(struct wm97xx *wm) wm 244 drivers/input/touchscreen/wm9712.c return wm->dig[2] & WM9712_PDEN; wm 250 drivers/input/touchscreen/wm9712.c static int wm9712_poll_sample(struct wm97xx *wm, int adcsel, int *sample) wm 255 drivers/input/touchscreen/wm9712.c if (wants_pen && !wm->pen_probably_down) { wm 256 drivers/input/touchscreen/wm9712.c u16 data = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 259 drivers/input/touchscreen/wm9712.c wm->pen_probably_down = 1; wm 263 drivers/input/touchscreen/wm9712.c if (wm->mach_ops && wm->mach_ops->pre_sample) wm 264 drivers/input/touchscreen/wm9712.c wm->mach_ops->pre_sample(adcsel); wm 265 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, (adcsel & WM97XX_ADCSEL_MASK) wm 272 drivers/input/touchscreen/wm9712.c while ((wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER1) & WM97XX_POLL) wm 280 drivers/input/touchscreen/wm9712.c if (is_pden(wm)) wm 281 drivers/input/touchscreen/wm9712.c wm->pen_probably_down = 0; wm 283 drivers/input/touchscreen/wm9712.c dev_dbg(wm->dev, "adc sample timeout\n"); wm 287 drivers/input/touchscreen/wm9712.c *sample = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 288 drivers/input/touchscreen/wm9712.c if (wm->mach_ops && wm->mach_ops->post_sample) wm 289 drivers/input/touchscreen/wm9712.c wm->mach_ops->post_sample(adcsel); wm 293 drivers/input/touchscreen/wm9712.c dev_dbg(wm->dev, "adc wrong sample, wanted %x got %x\n", wm 301 drivers/input/touchscreen/wm9712.c *sample = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 303 drivers/input/touchscreen/wm9712.c wm->pen_probably_down = 0; wm 314 drivers/input/touchscreen/wm9712.c static int wm9712_poll_coord(struct wm97xx *wm, struct wm97xx_data *data) wm 318 drivers/input/touchscreen/wm9712.c if (!wm->pen_probably_down) { wm 319 drivers/input/touchscreen/wm9712.c u16 data_rd = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 322 drivers/input/touchscreen/wm9712.c wm->pen_probably_down = 1; wm 326 drivers/input/touchscreen/wm9712.c if (wm->mach_ops && wm->mach_ops->pre_sample) wm 327 drivers/input/touchscreen/wm9712.c wm->mach_ops->pre_sample(WM97XX_ADCSEL_X | WM97XX_ADCSEL_Y); wm 329 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, wm 334 drivers/input/touchscreen/wm9712.c data->x = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 336 drivers/input/touchscreen/wm9712.c while ((wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER1) & WM97XX_POLL) wm 344 drivers/input/touchscreen/wm9712.c if (is_pden(wm)) wm 345 drivers/input/touchscreen/wm9712.c wm->pen_probably_down = 0; wm 347 drivers/input/touchscreen/wm9712.c dev_dbg(wm->dev, "adc sample timeout\n"); wm 352 drivers/input/touchscreen/wm9712.c data->y = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 354 drivers/input/touchscreen/wm9712.c data->p = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 358 drivers/input/touchscreen/wm9712.c if (wm->mach_ops && wm->mach_ops->post_sample) wm 359 drivers/input/touchscreen/wm9712.c wm->mach_ops->post_sample(WM97XX_ADCSEL_X | WM97XX_ADCSEL_Y); wm 368 drivers/input/touchscreen/wm9712.c wm->pen_probably_down = 0; wm 379 drivers/input/touchscreen/wm9712.c static int wm9712_poll_touch(struct wm97xx *wm, struct wm97xx_data *data) wm 384 drivers/input/touchscreen/wm9712.c rc = wm9712_poll_coord(wm, data); wm 388 drivers/input/touchscreen/wm9712.c rc = wm9712_poll_sample(wm, WM97XX_ADCSEL_X | WM97XX_PEN_DOWN, wm 393 drivers/input/touchscreen/wm9712.c rc = wm9712_poll_sample(wm, WM97XX_ADCSEL_Y | WM97XX_PEN_DOWN, wm 399 drivers/input/touchscreen/wm9712.c rc = wm9712_poll_sample(wm, WM97XX_ADCSEL_PRES | WM97XX_PEN_DOWN, wm 413 drivers/input/touchscreen/wm9712.c static int wm9712_acc_enable(struct wm97xx *wm, int enable) wm 418 drivers/input/touchscreen/wm9712.c dig1 = wm->dig[1]; wm 419 drivers/input/touchscreen/wm9712.c dig2 = wm->dig[2]; wm 423 drivers/input/touchscreen/wm9712.c if (wm->mach_ops->acc_startup) { wm 424 drivers/input/touchscreen/wm9712.c ret = wm->mach_ops->acc_startup(wm); wm 432 drivers/input/touchscreen/wm9712.c WM97XX_SLT(wm->acc_slot) | wm 433 drivers/input/touchscreen/wm9712.c WM97XX_RATE(wm->acc_rate); wm 440 drivers/input/touchscreen/wm9712.c if (wm->mach_ops->acc_shutdown) wm 441 drivers/input/touchscreen/wm9712.c wm->mach_ops->acc_shutdown(wm); wm 444 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER1, dig1); wm 445 drivers/input/touchscreen/wm9712.c wm97xx_reg_write(wm, AC97_WM97XX_DIGITISER2, dig2); wm 151 drivers/input/touchscreen/wm9713.c static void wm9713_phy_init(struct wm97xx *wm) wm 163 drivers/input/touchscreen/wm9713.c dev_info(wm->dev, "setting pen detect pull-up to %d Ohms\n", wm 170 drivers/input/touchscreen/wm9713.c dev_info(wm->dev, "setting 5-wire touchscreen mode."); wm 173 drivers/input/touchscreen/wm9713.c dev_warn(wm->dev, wm 183 drivers/input/touchscreen/wm9713.c dev_info(wm->dev, wm 186 drivers/input/touchscreen/wm9713.c dev_info(wm->dev, wm 193 drivers/input/touchscreen/wm9713.c dev_info(wm->dev, "supplied delay out of range."); wm 195 drivers/input/touchscreen/wm9713.c dev_info(wm->dev, "setting adc sample delay to %d u Secs.", wm 206 drivers/input/touchscreen/wm9713.c wm->misc = wm97xx_reg_read(wm, 0x5a); wm 208 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG1, dig1); wm 209 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG2, dig2); wm 210 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG3, dig3); wm 211 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_GPIO_STICKY, 0x0); wm 214 drivers/input/touchscreen/wm9713.c static void wm9713_dig_enable(struct wm97xx *wm, int enable) wm 219 drivers/input/touchscreen/wm9713.c val = wm97xx_reg_read(wm, AC97_EXTENDED_MID); wm 220 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, val & 0x7fff); wm 221 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG3, wm->dig[2] | wm 223 drivers/input/touchscreen/wm9713.c wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); /* dummy read */ wm 225 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG3, wm->dig[2] & wm 227 drivers/input/touchscreen/wm9713.c val = wm97xx_reg_read(wm, AC97_EXTENDED_MID); wm 228 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, val | 0x8000); wm 232 drivers/input/touchscreen/wm9713.c static void wm9713_dig_restore(struct wm97xx *wm) wm 234 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG1, wm->dig_save[0]); wm 235 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG2, wm->dig_save[1]); wm 236 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG3, wm->dig_save[2]); wm 239 drivers/input/touchscreen/wm9713.c static void wm9713_aux_prepare(struct wm97xx *wm) wm 241 drivers/input/touchscreen/wm9713.c memcpy(wm->dig_save, wm->dig, sizeof(wm->dig)); wm 242 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG1, 0); wm 243 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG2, 0); wm 244 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG3, WM97XX_PRP_DET_DIG); wm 247 drivers/input/touchscreen/wm9713.c static inline int is_pden(struct wm97xx *wm) wm 249 drivers/input/touchscreen/wm9713.c return wm->dig[2] & WM9713_PDEN; wm 255 drivers/input/touchscreen/wm9713.c static int wm9713_poll_sample(struct wm97xx *wm, int adcsel, int *sample) wm 261 drivers/input/touchscreen/wm9713.c if (wants_pen && !wm->pen_probably_down) { wm 262 drivers/input/touchscreen/wm9713.c u16 data = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 265 drivers/input/touchscreen/wm9713.c wm->pen_probably_down = 1; wm 269 drivers/input/touchscreen/wm9713.c dig1 = wm97xx_reg_read(wm, AC97_WM9713_DIG1); wm 274 drivers/input/touchscreen/wm9713.c if (wm->mach_ops && wm->mach_ops->pre_sample) wm 275 drivers/input/touchscreen/wm9713.c wm->mach_ops->pre_sample(adcsel); wm 276 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG1, dig1 | WM9713_POLL); wm 282 drivers/input/touchscreen/wm9713.c while ((wm97xx_reg_read(wm, AC97_WM9713_DIG1) & WM9713_POLL) && wm 290 drivers/input/touchscreen/wm9713.c if (is_pden(wm)) wm 291 drivers/input/touchscreen/wm9713.c wm->pen_probably_down = 0; wm 293 drivers/input/touchscreen/wm9713.c dev_dbg(wm->dev, "adc sample timeout"); wm 297 drivers/input/touchscreen/wm9713.c *sample = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 298 drivers/input/touchscreen/wm9713.c if (wm->mach_ops && wm->mach_ops->post_sample) wm 299 drivers/input/touchscreen/wm9713.c wm->mach_ops->post_sample(adcsel); wm 303 drivers/input/touchscreen/wm9713.c dev_dbg(wm->dev, "adc wrong sample, wanted %x got %x", wm 310 drivers/input/touchscreen/wm9713.c wm->pen_probably_down = 0; wm 320 drivers/input/touchscreen/wm9713.c static int wm9713_poll_coord(struct wm97xx *wm, struct wm97xx_data *data) wm 325 drivers/input/touchscreen/wm9713.c if (!wm->pen_probably_down) { wm 326 drivers/input/touchscreen/wm9713.c u16 val = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 329 drivers/input/touchscreen/wm9713.c wm->pen_probably_down = 1; wm 333 drivers/input/touchscreen/wm9713.c dig1 = wm97xx_reg_read(wm, AC97_WM9713_DIG1); wm 338 drivers/input/touchscreen/wm9713.c if (wm->mach_ops && wm->mach_ops->pre_sample) wm 339 drivers/input/touchscreen/wm9713.c wm->mach_ops->pre_sample(WM97XX_ADCSEL_X | WM97XX_ADCSEL_Y); wm 340 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG1, wm 345 drivers/input/touchscreen/wm9713.c data->x = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 347 drivers/input/touchscreen/wm9713.c while ((wm97xx_reg_read(wm, AC97_WM9713_DIG1) & WM9713_POLL) wm 355 drivers/input/touchscreen/wm9713.c if (is_pden(wm)) wm 356 drivers/input/touchscreen/wm9713.c wm->pen_probably_down = 0; wm 358 drivers/input/touchscreen/wm9713.c dev_dbg(wm->dev, "adc sample timeout"); wm 363 drivers/input/touchscreen/wm9713.c data->y = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 365 drivers/input/touchscreen/wm9713.c data->p = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD); wm 369 drivers/input/touchscreen/wm9713.c if (wm->mach_ops && wm->mach_ops->post_sample) wm 370 drivers/input/touchscreen/wm9713.c wm->mach_ops->post_sample(WM97XX_ADCSEL_X | WM97XX_ADCSEL_Y); wm 379 drivers/input/touchscreen/wm9713.c wm->pen_probably_down = 0; wm 390 drivers/input/touchscreen/wm9713.c static int wm9713_poll_touch(struct wm97xx *wm, struct wm97xx_data *data) wm 395 drivers/input/touchscreen/wm9713.c rc = wm9713_poll_coord(wm, data); wm 399 drivers/input/touchscreen/wm9713.c rc = wm9713_poll_sample(wm, WM97XX_ADCSEL_X | WM97XX_PEN_DOWN, &data->x); wm 402 drivers/input/touchscreen/wm9713.c rc = wm9713_poll_sample(wm, WM97XX_ADCSEL_Y | WM97XX_PEN_DOWN, &data->y); wm 406 drivers/input/touchscreen/wm9713.c rc = wm9713_poll_sample(wm, WM97XX_ADCSEL_PRES | WM97XX_PEN_DOWN, wm 420 drivers/input/touchscreen/wm9713.c static int wm9713_acc_enable(struct wm97xx *wm, int enable) wm 425 drivers/input/touchscreen/wm9713.c dig1 = wm->dig[0]; wm 426 drivers/input/touchscreen/wm9713.c dig2 = wm->dig[1]; wm 427 drivers/input/touchscreen/wm9713.c dig3 = wm->dig[2]; wm 431 drivers/input/touchscreen/wm9713.c if (wm->mach_ops->acc_startup && wm 432 drivers/input/touchscreen/wm9713.c (ret = wm->mach_ops->acc_startup(wm)) < 0) wm 443 drivers/input/touchscreen/wm9713.c WM97XX_SLT(wm->acc_slot) | WM97XX_RATE(wm->acc_rate); wm 449 drivers/input/touchscreen/wm9713.c if (wm->mach_ops->acc_shutdown) wm 450 drivers/input/touchscreen/wm9713.c wm->mach_ops->acc_shutdown(wm); wm 453 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG1, dig1); wm 454 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG2, dig2); wm 455 drivers/input/touchscreen/wm9713.c wm97xx_reg_write(wm, AC97_WM9713_DIG3, dig3); wm 84 drivers/input/touchscreen/wm97xx-core.c int wm97xx_reg_read(struct wm97xx *wm, u16 reg) wm 86 drivers/input/touchscreen/wm97xx-core.c if (wm->ac97) wm 87 drivers/input/touchscreen/wm97xx-core.c return wm->ac97->bus->ops->read(wm->ac97, reg); wm 93 drivers/input/touchscreen/wm97xx-core.c void wm97xx_reg_write(struct wm97xx *wm, u16 reg, u16 val) wm 97 drivers/input/touchscreen/wm97xx-core.c wm->dig[(reg - AC97_WM9713_DIG1) >> 1] = val; wm 101 drivers/input/touchscreen/wm97xx-core.c wm->gpio[(reg - AC97_GPIO_CFG) >> 1] = val; wm 105 drivers/input/touchscreen/wm97xx-core.c wm->misc = val; wm 107 drivers/input/touchscreen/wm97xx-core.c if (wm->ac97) wm 108 drivers/input/touchscreen/wm97xx-core.c wm->ac97->bus->ops->write(wm->ac97, reg, val); wm 120 drivers/input/touchscreen/wm97xx-core.c int wm97xx_read_aux_adc(struct wm97xx *wm, u16 adcsel) wm 128 drivers/input/touchscreen/wm97xx-core.c mutex_lock(&wm->codec_mutex); wm 133 drivers/input/touchscreen/wm97xx-core.c if (wm->id == WM9713_ID2 && wm 134 drivers/input/touchscreen/wm97xx-core.c (power = wm97xx_reg_read(wm, AC97_EXTENDED_MID)) & 0x8000) { wm 136 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, power & 0x7fff); wm 140 drivers/input/touchscreen/wm97xx-core.c wm->codec->aux_prepare(wm); wm 143 drivers/input/touchscreen/wm97xx-core.c wm->pen_probably_down = 1; wm 146 drivers/input/touchscreen/wm97xx-core.c rc = wm->codec->poll_sample(wm, adcsel, &auxval); wm 149 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, power | 0x8000); wm 151 drivers/input/touchscreen/wm97xx-core.c wm->codec->dig_restore(wm); wm 153 drivers/input/touchscreen/wm97xx-core.c wm->pen_probably_down = 0; wm 156 drivers/input/touchscreen/wm97xx-core.c dev_err(wm->dev, wm 159 drivers/input/touchscreen/wm97xx-core.c wm->codec->dig_enable(wm, false); wm 162 drivers/input/touchscreen/wm97xx-core.c mutex_unlock(&wm->codec_mutex); wm 175 drivers/input/touchscreen/wm97xx-core.c enum wm97xx_gpio_status wm97xx_get_gpio(struct wm97xx *wm, u32 gpio) wm 180 drivers/input/touchscreen/wm97xx-core.c mutex_lock(&wm->codec_mutex); wm 181 drivers/input/touchscreen/wm97xx-core.c status = wm97xx_reg_read(wm, AC97_GPIO_STATUS); wm 188 drivers/input/touchscreen/wm97xx-core.c mutex_unlock(&wm->codec_mutex); wm 202 drivers/input/touchscreen/wm97xx-core.c void wm97xx_set_gpio(struct wm97xx *wm, u32 gpio, wm 207 drivers/input/touchscreen/wm97xx-core.c mutex_lock(&wm->codec_mutex); wm 208 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_STATUS); wm 215 drivers/input/touchscreen/wm97xx-core.c if (wm->id == WM9712_ID2 && wm->variant != WM97xx_WM1613) wm 216 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STATUS, reg << 1); wm 218 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STATUS, reg); wm 219 drivers/input/touchscreen/wm97xx-core.c mutex_unlock(&wm->codec_mutex); wm 227 drivers/input/touchscreen/wm97xx-core.c void wm97xx_config_gpio(struct wm97xx *wm, u32 gpio, enum wm97xx_gpio_dir dir, wm 233 drivers/input/touchscreen/wm97xx-core.c mutex_lock(&wm->codec_mutex); wm 234 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_POLARITY); wm 241 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_POLARITY, reg); wm 242 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_STICKY); wm 249 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STICKY, reg); wm 250 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_WAKEUP); wm 257 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_WAKEUP, reg); wm 258 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_GPIO_CFG); wm 265 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_CFG, reg); wm 266 drivers/input/touchscreen/wm97xx-core.c mutex_unlock(&wm->codec_mutex); wm 280 drivers/input/touchscreen/wm97xx-core.c void wm97xx_set_suspend_mode(struct wm97xx *wm, u16 mode) wm 282 drivers/input/touchscreen/wm97xx-core.c wm->suspend_mode = mode; wm 283 drivers/input/touchscreen/wm97xx-core.c device_init_wakeup(&wm->input_dev->dev, mode != 0); wm 292 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm = container_of(work, struct wm97xx, pen_event_work); wm 293 drivers/input/touchscreen/wm97xx-core.c int pen_was_down = wm->pen_is_down; wm 296 drivers/input/touchscreen/wm97xx-core.c if (wm->id == WM9705_ID2) { wm 297 drivers/input/touchscreen/wm97xx-core.c if (wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER_RD) & wm 299 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 1; wm 301 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 0; wm 304 drivers/input/touchscreen/wm97xx-core.c mutex_lock(&wm->codec_mutex); wm 305 drivers/input/touchscreen/wm97xx-core.c status = wm97xx_reg_read(wm, AC97_GPIO_STATUS); wm 306 drivers/input/touchscreen/wm97xx-core.c pol = wm97xx_reg_read(wm, AC97_GPIO_POLARITY); wm 309 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 1; wm 310 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_POLARITY, pol & wm 313 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 0; wm 314 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_POLARITY, pol | wm 318 drivers/input/touchscreen/wm97xx-core.c if (wm->id == WM9712_ID2 && wm->variant != WM97xx_WM1613) wm 319 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STATUS, (status & wm 322 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STATUS, status & wm 324 drivers/input/touchscreen/wm97xx-core.c mutex_unlock(&wm->codec_mutex); wm 332 drivers/input/touchscreen/wm97xx-core.c if (!wm->mach_ops->acc_enabled || wm->mach_ops->acc_pen_down) { wm 333 drivers/input/touchscreen/wm97xx-core.c if (wm->pen_is_down && !pen_was_down) { wm 335 drivers/input/touchscreen/wm97xx-core.c queue_delayed_work(wm->ts_workq, &wm->ts_reader, 1); wm 339 drivers/input/touchscreen/wm97xx-core.c if (!wm->pen_is_down && pen_was_down) wm 340 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 1; wm 343 drivers/input/touchscreen/wm97xx-core.c if (!wm->pen_is_down && wm->mach_ops->acc_enabled) wm 344 drivers/input/touchscreen/wm97xx-core.c wm->mach_ops->acc_pen_up(wm); wm 346 drivers/input/touchscreen/wm97xx-core.c wm->mach_ops->irq_enable(wm, 1); wm 360 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm = dev_id; wm 362 drivers/input/touchscreen/wm97xx-core.c if (!work_pending(&wm->pen_event_work)) { wm 363 drivers/input/touchscreen/wm97xx-core.c wm->mach_ops->irq_enable(wm, 0); wm 364 drivers/input/touchscreen/wm97xx-core.c queue_work(wm->ts_workq, &wm->pen_event_work); wm 373 drivers/input/touchscreen/wm97xx-core.c static int wm97xx_init_pen_irq(struct wm97xx *wm) wm 379 drivers/input/touchscreen/wm97xx-core.c BUG_ON(!wm->mach_ops->irq_enable); wm 381 drivers/input/touchscreen/wm97xx-core.c if (request_irq(wm->pen_irq, wm97xx_pen_interrupt, IRQF_SHARED, wm 382 drivers/input/touchscreen/wm97xx-core.c "wm97xx-pen", wm)) { wm 383 drivers/input/touchscreen/wm97xx-core.c dev_err(wm->dev, wm 385 drivers/input/touchscreen/wm97xx-core.c wm->pen_irq = 0; wm 390 drivers/input/touchscreen/wm97xx-core.c if (wm->id != WM9705_ID2) { wm 391 drivers/input/touchscreen/wm97xx-core.c BUG_ON(!wm->mach_ops->irq_gpio); wm 392 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_MISC_AFE); wm 393 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_MISC_AFE, wm 394 drivers/input/touchscreen/wm97xx-core.c reg & ~(wm->mach_ops->irq_gpio)); wm 395 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, 0x5a); wm 396 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, 0x5a, reg & ~0x0001); wm 402 drivers/input/touchscreen/wm97xx-core.c static int wm97xx_read_samples(struct wm97xx *wm) wm 407 drivers/input/touchscreen/wm97xx-core.c mutex_lock(&wm->codec_mutex); wm 409 drivers/input/touchscreen/wm97xx-core.c if (wm->mach_ops && wm->mach_ops->acc_enabled) wm 410 drivers/input/touchscreen/wm97xx-core.c rc = wm->mach_ops->acc_pen_down(wm); wm 412 drivers/input/touchscreen/wm97xx-core.c rc = wm->codec->poll_touch(wm, &data); wm 415 drivers/input/touchscreen/wm97xx-core.c if (wm->pen_is_down) { wm 416 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 0; wm 417 drivers/input/touchscreen/wm97xx-core.c dev_dbg(wm->dev, "pen up\n"); wm 418 drivers/input/touchscreen/wm97xx-core.c input_report_abs(wm->input_dev, ABS_PRESSURE, 0); wm 419 drivers/input/touchscreen/wm97xx-core.c input_report_key(wm->input_dev, BTN_TOUCH, 0); wm 420 drivers/input/touchscreen/wm97xx-core.c input_sync(wm->input_dev); wm 432 drivers/input/touchscreen/wm97xx-core.c if (wm->ts_reader_interval < HZ / 10) wm 433 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_interval++; wm 437 drivers/input/touchscreen/wm97xx-core.c dev_dbg(wm->dev, wm 446 drivers/input/touchscreen/wm97xx-core.c dev_dbg(wm->dev, "Measurement out of range, dropping it\n"); wm 451 drivers/input/touchscreen/wm97xx-core.c input_report_abs(wm->input_dev, ABS_X, data.x & 0xfff); wm 452 drivers/input/touchscreen/wm97xx-core.c input_report_abs(wm->input_dev, ABS_Y, data.y & 0xfff); wm 453 drivers/input/touchscreen/wm97xx-core.c input_report_abs(wm->input_dev, ABS_PRESSURE, data.p & 0xfff); wm 454 drivers/input/touchscreen/wm97xx-core.c input_report_key(wm->input_dev, BTN_TOUCH, 1); wm 455 drivers/input/touchscreen/wm97xx-core.c input_sync(wm->input_dev); wm 456 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 1; wm 457 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_interval = wm->ts_reader_min_interval; wm 459 drivers/input/touchscreen/wm97xx-core.c dev_dbg(wm->dev, "pen down\n"); wm 460 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 1; wm 461 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_interval = wm->ts_reader_min_interval; wm 465 drivers/input/touchscreen/wm97xx-core.c mutex_unlock(&wm->codec_mutex); wm 475 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm = container_of(work, struct wm97xx, ts_reader.work); wm 477 drivers/input/touchscreen/wm97xx-core.c BUG_ON(!wm->codec); wm 480 drivers/input/touchscreen/wm97xx-core.c rc = wm97xx_read_samples(wm); wm 483 drivers/input/touchscreen/wm97xx-core.c if (wm->pen_is_down || !wm->pen_irq) wm 484 drivers/input/touchscreen/wm97xx-core.c queue_delayed_work(wm->ts_workq, &wm->ts_reader, wm 485 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_interval); wm 497 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm = input_get_drvdata(idev); wm 499 drivers/input/touchscreen/wm97xx-core.c wm->ts_workq = alloc_ordered_workqueue("kwm97xx", 0); wm 500 drivers/input/touchscreen/wm97xx-core.c if (wm->ts_workq == NULL) { wm 501 drivers/input/touchscreen/wm97xx-core.c dev_err(wm->dev, wm 507 drivers/input/touchscreen/wm97xx-core.c if (wm->mach_ops && wm->mach_ops->acc_enabled) wm 508 drivers/input/touchscreen/wm97xx-core.c wm->codec->acc_enable(wm, 1); wm 509 drivers/input/touchscreen/wm97xx-core.c wm->codec->dig_enable(wm, 1); wm 511 drivers/input/touchscreen/wm97xx-core.c INIT_DELAYED_WORK(&wm->ts_reader, wm97xx_ts_reader); wm 512 drivers/input/touchscreen/wm97xx-core.c INIT_WORK(&wm->pen_event_work, wm97xx_pen_irq_worker); wm 514 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_min_interval = HZ >= 100 ? HZ / 100 : 1; wm 515 drivers/input/touchscreen/wm97xx-core.c if (wm->ts_reader_min_interval < 1) wm 516 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_min_interval = 1; wm 517 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_interval = wm->ts_reader_min_interval; wm 519 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 0; wm 520 drivers/input/touchscreen/wm97xx-core.c if (wm->pen_irq) wm 521 drivers/input/touchscreen/wm97xx-core.c wm97xx_init_pen_irq(wm); wm 523 drivers/input/touchscreen/wm97xx-core.c dev_err(wm->dev, "No IRQ specified\n"); wm 528 drivers/input/touchscreen/wm97xx-core.c if (wm->pen_irq == 0) wm 529 drivers/input/touchscreen/wm97xx-core.c queue_delayed_work(wm->ts_workq, &wm->ts_reader, wm 530 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_interval); wm 546 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm = input_get_drvdata(idev); wm 549 drivers/input/touchscreen/wm97xx-core.c if (wm->pen_irq) { wm 551 drivers/input/touchscreen/wm97xx-core.c if (wm->id != WM9705_ID2) { wm 552 drivers/input/touchscreen/wm97xx-core.c BUG_ON(!wm->mach_ops->irq_gpio); wm 553 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_MISC_AFE); wm 554 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_MISC_AFE, wm 555 drivers/input/touchscreen/wm97xx-core.c reg | wm->mach_ops->irq_gpio); wm 558 drivers/input/touchscreen/wm97xx-core.c free_irq(wm->pen_irq, wm); wm 561 drivers/input/touchscreen/wm97xx-core.c wm->pen_is_down = 0; wm 564 drivers/input/touchscreen/wm97xx-core.c if (cancel_work_sync(&wm->pen_event_work)) wm 565 drivers/input/touchscreen/wm97xx-core.c wm->mach_ops->irq_enable(wm, 1); wm 570 drivers/input/touchscreen/wm97xx-core.c cancel_delayed_work_sync(&wm->ts_reader); wm 572 drivers/input/touchscreen/wm97xx-core.c destroy_workqueue(wm->ts_workq); wm 575 drivers/input/touchscreen/wm97xx-core.c wm->codec->dig_enable(wm, 0); wm 576 drivers/input/touchscreen/wm97xx-core.c if (wm->mach_ops && wm->mach_ops->acc_enabled) wm 577 drivers/input/touchscreen/wm97xx-core.c wm->codec->acc_enable(wm, 0); wm 580 drivers/input/touchscreen/wm97xx-core.c static int wm97xx_register_touch(struct wm97xx *wm) wm 582 drivers/input/touchscreen/wm97xx-core.c struct wm97xx_pdata *pdata = dev_get_platdata(wm->dev); wm 585 drivers/input/touchscreen/wm97xx-core.c wm->input_dev = devm_input_allocate_device(wm->dev); wm 586 drivers/input/touchscreen/wm97xx-core.c if (wm->input_dev == NULL) wm 590 drivers/input/touchscreen/wm97xx-core.c wm->input_dev->name = "wm97xx touchscreen"; wm 591 drivers/input/touchscreen/wm97xx-core.c wm->input_dev->phys = "wm97xx"; wm 592 drivers/input/touchscreen/wm97xx-core.c wm->input_dev->open = wm97xx_ts_input_open; wm 593 drivers/input/touchscreen/wm97xx-core.c wm->input_dev->close = wm97xx_ts_input_close; wm 595 drivers/input/touchscreen/wm97xx-core.c __set_bit(EV_ABS, wm->input_dev->evbit); wm 596 drivers/input/touchscreen/wm97xx-core.c __set_bit(EV_KEY, wm->input_dev->evbit); wm 597 drivers/input/touchscreen/wm97xx-core.c __set_bit(BTN_TOUCH, wm->input_dev->keybit); wm 599 drivers/input/touchscreen/wm97xx-core.c input_set_abs_params(wm->input_dev, ABS_X, abs_x[0], abs_x[1], wm 601 drivers/input/touchscreen/wm97xx-core.c input_set_abs_params(wm->input_dev, ABS_Y, abs_y[0], abs_y[1], wm 603 drivers/input/touchscreen/wm97xx-core.c input_set_abs_params(wm->input_dev, ABS_PRESSURE, abs_p[0], abs_p[1], wm 606 drivers/input/touchscreen/wm97xx-core.c input_set_drvdata(wm->input_dev, wm); wm 607 drivers/input/touchscreen/wm97xx-core.c wm->input_dev->dev.parent = wm->dev; wm 609 drivers/input/touchscreen/wm97xx-core.c ret = input_register_device(wm->input_dev); wm 617 drivers/input/touchscreen/wm97xx-core.c wm->touch_dev = platform_device_alloc("wm97xx-touch", -1); wm 618 drivers/input/touchscreen/wm97xx-core.c if (!wm->touch_dev) { wm 622 drivers/input/touchscreen/wm97xx-core.c platform_set_drvdata(wm->touch_dev, wm); wm 623 drivers/input/touchscreen/wm97xx-core.c wm->touch_dev->dev.parent = wm->dev; wm 624 drivers/input/touchscreen/wm97xx-core.c wm->touch_dev->dev.platform_data = pdata; wm 625 drivers/input/touchscreen/wm97xx-core.c ret = platform_device_add(wm->touch_dev); wm 631 drivers/input/touchscreen/wm97xx-core.c platform_device_put(wm->touch_dev); wm 633 drivers/input/touchscreen/wm97xx-core.c input_unregister_device(wm->input_dev); wm 634 drivers/input/touchscreen/wm97xx-core.c wm->input_dev = NULL; wm 639 drivers/input/touchscreen/wm97xx-core.c static void wm97xx_unregister_touch(struct wm97xx *wm) wm 641 drivers/input/touchscreen/wm97xx-core.c platform_device_unregister(wm->touch_dev); wm 642 drivers/input/touchscreen/wm97xx-core.c input_unregister_device(wm->input_dev); wm 643 drivers/input/touchscreen/wm97xx-core.c wm->input_dev = NULL; wm 646 drivers/input/touchscreen/wm97xx-core.c static int _wm97xx_probe(struct wm97xx *wm) wm 650 drivers/input/touchscreen/wm97xx-core.c mutex_init(&wm->codec_mutex); wm 651 drivers/input/touchscreen/wm97xx-core.c dev_set_drvdata(wm->dev, wm); wm 654 drivers/input/touchscreen/wm97xx-core.c id = wm97xx_reg_read(wm, AC97_VENDOR_ID1); wm 656 drivers/input/touchscreen/wm97xx-core.c dev_err(wm->dev, wm 661 drivers/input/touchscreen/wm97xx-core.c wm->id = wm97xx_reg_read(wm, AC97_VENDOR_ID2); wm 663 drivers/input/touchscreen/wm97xx-core.c wm->variant = WM97xx_GENERIC; wm 665 drivers/input/touchscreen/wm97xx-core.c dev_info(wm->dev, "detected a wm97%02x codec\n", wm->id & 0xff); wm 667 drivers/input/touchscreen/wm97xx-core.c switch (wm->id & 0xff) { wm 670 drivers/input/touchscreen/wm97xx-core.c wm->codec = &wm9705_codec; wm 675 drivers/input/touchscreen/wm97xx-core.c wm->codec = &wm9712_codec; wm 680 drivers/input/touchscreen/wm97xx-core.c wm->codec = &wm9713_codec; wm 684 drivers/input/touchscreen/wm97xx-core.c dev_err(wm->dev, "Support for wm97%02x not compiled in.\n", wm 685 drivers/input/touchscreen/wm97xx-core.c wm->id & 0xff); wm 690 drivers/input/touchscreen/wm97xx-core.c wm->codec->phy_init(wm); wm 693 drivers/input/touchscreen/wm97xx-core.c wm->gpio[0] = wm97xx_reg_read(wm, AC97_GPIO_CFG); wm 694 drivers/input/touchscreen/wm97xx-core.c wm->gpio[1] = wm97xx_reg_read(wm, AC97_GPIO_POLARITY); wm 695 drivers/input/touchscreen/wm97xx-core.c wm->gpio[2] = wm97xx_reg_read(wm, AC97_GPIO_STICKY); wm 696 drivers/input/touchscreen/wm97xx-core.c wm->gpio[3] = wm97xx_reg_read(wm, AC97_GPIO_WAKEUP); wm 697 drivers/input/touchscreen/wm97xx-core.c wm->gpio[4] = wm97xx_reg_read(wm, AC97_GPIO_STATUS); wm 698 drivers/input/touchscreen/wm97xx-core.c wm->gpio[5] = wm97xx_reg_read(wm, AC97_MISC_AFE); wm 700 drivers/input/touchscreen/wm97xx-core.c return wm97xx_register_touch(wm); wm 703 drivers/input/touchscreen/wm97xx-core.c static void wm97xx_remove_battery(struct wm97xx *wm) wm 705 drivers/input/touchscreen/wm97xx-core.c platform_device_unregister(wm->battery_dev); wm 708 drivers/input/touchscreen/wm97xx-core.c static int wm97xx_add_battery(struct wm97xx *wm, wm 713 drivers/input/touchscreen/wm97xx-core.c wm->battery_dev = platform_device_alloc("wm97xx-battery", -1); wm 714 drivers/input/touchscreen/wm97xx-core.c if (!wm->battery_dev) wm 717 drivers/input/touchscreen/wm97xx-core.c platform_set_drvdata(wm->battery_dev, wm); wm 718 drivers/input/touchscreen/wm97xx-core.c wm->battery_dev->dev.parent = wm->dev; wm 719 drivers/input/touchscreen/wm97xx-core.c wm->battery_dev->dev.platform_data = pdata; wm 720 drivers/input/touchscreen/wm97xx-core.c ret = platform_device_add(wm->battery_dev); wm 722 drivers/input/touchscreen/wm97xx-core.c platform_device_put(wm->battery_dev); wm 729 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm; wm 733 drivers/input/touchscreen/wm97xx-core.c wm = devm_kzalloc(dev, sizeof(struct wm97xx), GFP_KERNEL); wm 734 drivers/input/touchscreen/wm97xx-core.c if (!wm) wm 737 drivers/input/touchscreen/wm97xx-core.c wm->dev = dev; wm 738 drivers/input/touchscreen/wm97xx-core.c wm->ac97 = to_ac97_t(dev); wm 740 drivers/input/touchscreen/wm97xx-core.c ret = _wm97xx_probe(wm); wm 744 drivers/input/touchscreen/wm97xx-core.c ret = wm97xx_add_battery(wm, pdata ? pdata->batt_pdata : NULL); wm 751 drivers/input/touchscreen/wm97xx-core.c wm97xx_unregister_touch(wm); wm 757 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm = dev_get_drvdata(dev); wm 759 drivers/input/touchscreen/wm97xx-core.c wm97xx_remove_battery(wm); wm 760 drivers/input/touchscreen/wm97xx-core.c wm97xx_unregister_touch(wm); wm 767 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm; wm 771 drivers/input/touchscreen/wm97xx-core.c wm = devm_kzalloc(&pdev->dev, sizeof(struct wm97xx), GFP_KERNEL); wm 772 drivers/input/touchscreen/wm97xx-core.c if (!wm) wm 775 drivers/input/touchscreen/wm97xx-core.c wm->dev = &pdev->dev; wm 776 drivers/input/touchscreen/wm97xx-core.c wm->ac97 = mfd_pdata->ac97; wm 778 drivers/input/touchscreen/wm97xx-core.c ret = _wm97xx_probe(wm); wm 782 drivers/input/touchscreen/wm97xx-core.c ret = wm97xx_add_battery(wm, mfd_pdata->batt_pdata); wm 789 drivers/input/touchscreen/wm97xx-core.c wm97xx_unregister_touch(wm); wm 800 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm = dev_get_drvdata(dev); wm 804 drivers/input/touchscreen/wm97xx-core.c if (device_may_wakeup(&wm->input_dev->dev)) wm 805 drivers/input/touchscreen/wm97xx-core.c suspend_mode = wm->suspend_mode; wm 809 drivers/input/touchscreen/wm97xx-core.c if (wm->input_dev->users) wm 810 drivers/input/touchscreen/wm97xx-core.c cancel_delayed_work_sync(&wm->ts_reader); wm 813 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_WM97XX_DIGITISER2); wm 815 drivers/input/touchscreen/wm97xx-core.c if (wm->input_dev->users) wm 817 drivers/input/touchscreen/wm97xx-core.c wm->ac97->bus->ops->write(wm->ac97, AC97_WM97XX_DIGITISER2, reg); wm 821 drivers/input/touchscreen/wm97xx-core.c if (wm->id == WM9713_ID2 && wm 822 drivers/input/touchscreen/wm97xx-core.c (!wm->input_dev->users || !suspend_mode)) { wm 823 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_EXTENDED_MID) | 0x8000; wm 824 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, reg); wm 832 drivers/input/touchscreen/wm97xx-core.c struct wm97xx *wm = dev_get_drvdata(dev); wm 835 drivers/input/touchscreen/wm97xx-core.c if (wm->id == WM9713_ID2) { wm 836 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_WM9713_DIG1, wm->dig[0]); wm 837 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, 0x5a, wm->misc); wm 838 drivers/input/touchscreen/wm97xx-core.c if (wm->input_dev->users) { wm 840 drivers/input/touchscreen/wm97xx-core.c reg = wm97xx_reg_read(wm, AC97_EXTENDED_MID) & 0x7fff; wm 841 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_EXTENDED_MID, reg); wm 845 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_WM9713_DIG2, wm->dig[1]); wm 846 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_WM9713_DIG3, wm->dig[2]); wm 848 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_CFG, wm->gpio[0]); wm 849 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_POLARITY, wm->gpio[1]); wm 850 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STICKY, wm->gpio[2]); wm 851 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_WAKEUP, wm->gpio[3]); wm 852 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_GPIO_STATUS, wm->gpio[4]); wm 853 drivers/input/touchscreen/wm97xx-core.c wm97xx_reg_write(wm, AC97_MISC_AFE, wm->gpio[5]); wm 855 drivers/input/touchscreen/wm97xx-core.c if (wm->input_dev->users && !wm->pen_irq) { wm 856 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_interval = wm->ts_reader_min_interval; wm 857 drivers/input/touchscreen/wm97xx-core.c queue_delayed_work(wm->ts_workq, &wm->ts_reader, wm 858 drivers/input/touchscreen/wm97xx-core.c wm->ts_reader_interval); wm 869 drivers/input/touchscreen/wm97xx-core.c int wm97xx_register_mach_ops(struct wm97xx *wm, wm 872 drivers/input/touchscreen/wm97xx-core.c mutex_lock(&wm->codec_mutex); wm 873 drivers/input/touchscreen/wm97xx-core.c if (wm->mach_ops) { wm 874 drivers/input/touchscreen/wm97xx-core.c mutex_unlock(&wm->codec_mutex); wm 877 drivers/input/touchscreen/wm97xx-core.c wm->mach_ops = mach_ops; wm 878 drivers/input/touchscreen/wm97xx-core.c mutex_unlock(&wm->codec_mutex); wm 884 drivers/input/touchscreen/wm97xx-core.c void wm97xx_unregister_mach_ops(struct wm97xx *wm) wm 886 drivers/input/touchscreen/wm97xx-core.c mutex_lock(&wm->codec_mutex); wm 887 drivers/input/touchscreen/wm97xx-core.c wm->mach_ops = NULL; wm 888 drivers/input/touchscreen/wm97xx-core.c mutex_unlock(&wm->codec_mutex); wm 76 drivers/input/touchscreen/zylonite-wm97xx.c static void wm97xx_acc_pen_up(struct wm97xx *wm) wm 86 drivers/input/touchscreen/zylonite-wm97xx.c static int wm97xx_acc_pen_down(struct wm97xx *wm) wm 117 drivers/input/touchscreen/zylonite-wm97xx.c dev_dbg(wm->dev, "Raw coordinates: x=%x, y=%x, p=%x\n", wm 128 drivers/input/touchscreen/zylonite-wm97xx.c input_report_abs(wm->input_dev, ABS_X, x & 0xfff); wm 129 drivers/input/touchscreen/zylonite-wm97xx.c input_report_abs(wm->input_dev, ABS_Y, y & 0xfff); wm 130 drivers/input/touchscreen/zylonite-wm97xx.c input_report_abs(wm->input_dev, ABS_PRESSURE, p & 0xfff); wm 131 drivers/input/touchscreen/zylonite-wm97xx.c input_report_key(wm->input_dev, BTN_TOUCH, (p != 0)); wm 132 drivers/input/touchscreen/zylonite-wm97xx.c input_sync(wm->input_dev); wm 139 drivers/input/touchscreen/zylonite-wm97xx.c static int wm97xx_acc_startup(struct wm97xx *wm) wm 144 drivers/input/touchscreen/zylonite-wm97xx.c if (wm->ac97 == NULL) wm 149 drivers/input/touchscreen/zylonite-wm97xx.c if (wm->id != cinfo[idx].id) wm 155 drivers/input/touchscreen/zylonite-wm97xx.c wm->acc_rate = cinfo[sp_idx].code; wm 156 drivers/input/touchscreen/zylonite-wm97xx.c wm->acc_slot = ac97_touch_slot; wm 157 drivers/input/touchscreen/zylonite-wm97xx.c dev_info(wm->dev, wm 164 drivers/input/touchscreen/zylonite-wm97xx.c static void wm97xx_irq_enable(struct wm97xx *wm, int enable) wm 167 drivers/input/touchscreen/zylonite-wm97xx.c enable_irq(wm->pen_irq); wm 169 drivers/input/touchscreen/zylonite-wm97xx.c disable_irq_nosync(wm->pen_irq); wm 183 drivers/input/touchscreen/zylonite-wm97xx.c struct wm97xx *wm = platform_get_drvdata(pdev); wm 191 drivers/input/touchscreen/zylonite-wm97xx.c wm->pen_irq = gpio_to_irq(gpio_touch_irq); wm 192 drivers/input/touchscreen/zylonite-wm97xx.c irq_set_irq_type(wm->pen_irq, IRQ_TYPE_EDGE_BOTH); wm 194 drivers/input/touchscreen/zylonite-wm97xx.c wm97xx_config_gpio(wm, WM97XX_GPIO_13, WM97XX_GPIO_IN, wm 198 drivers/input/touchscreen/zylonite-wm97xx.c wm97xx_config_gpio(wm, WM97XX_GPIO_2, WM97XX_GPIO_OUT, wm 203 drivers/input/touchscreen/zylonite-wm97xx.c return wm97xx_register_mach_ops(wm, &zylonite_mach_ops); wm 208 drivers/input/touchscreen/zylonite-wm97xx.c struct wm97xx *wm = platform_get_drvdata(pdev); wm 210 drivers/input/touchscreen/zylonite-wm97xx.c wm97xx_unregister_mach_ops(wm); wm 266 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) wm 269 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), wm 272 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), wm 276 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) wm 279 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), wm 282 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), wm 331 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, wm 348 drivers/media/platform/qcom/camss/camss-vfe-4-1.c VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); wm 357 drivers/media/platform/qcom/camss/camss-vfe-4-1.c VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); wm 360 drivers/media/platform/qcom/camss/camss-vfe-4-1.c VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); wm 362 drivers/media/platform/qcom/camss/camss-vfe-4-1.c VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); wm 366 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) wm 371 drivers/media/platform/qcom/camss/camss-vfe-4-1.c VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); wm 379 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); wm 382 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, wm 386 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); wm 389 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, wm 396 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); wm 399 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) wm 402 drivers/media/platform/qcom/camss/camss-vfe-4-1.c writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); wm 406 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) wm 409 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); wm 412 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) wm 415 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); wm 418 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) wm 424 drivers/media/platform/qcom/camss/camss-vfe-4-1.c return (reg >> wm) & 0x1; wm 435 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, wm 465 drivers/media/platform/qcom/camss/camss-vfe-4-1.c if (wm % 2 == 1) wm 468 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); wm 471 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) wm 475 drivers/media/platform/qcom/camss/camss-vfe-4-1.c VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); wm 478 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, wm 505 drivers/media/platform/qcom/camss/camss-vfe-4-1.c if (wm % 2 == 1) wm 508 drivers/media/platform/qcom/camss/camss-vfe-4-1.c vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); wm 574 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, wm 577 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | wm 579 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | wm 803 drivers/media/platform/qcom/camss/camss-vfe-4-1.c static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) wm 805 drivers/media/platform/qcom/camss/camss-vfe-4-1.c u32 val = VFE_0_CGC_OVERRIDE_1_IMAGE_Mx_CGC_OVERRIDE(wm); wm 302 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_wm_enable(struct vfe_device *vfe, u8 wm, u8 enable) wm 305 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), wm 308 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(wm), wm 312 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_wm_frame_based(struct vfe_device *vfe, u8 wm, u8 enable) wm 315 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_set(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), wm 318 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_clr(vfe, VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm), wm 381 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_wm_line_based(struct vfe_device *vfe, u32 wm, wm 398 drivers/media/platform/qcom/camss/camss-vfe-4-7.c VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); wm 407 drivers/media/platform/qcom/camss/camss-vfe-4-7.c VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); wm 410 drivers/media/platform/qcom/camss/camss-vfe-4-7.c VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(wm)); wm 412 drivers/media/platform/qcom/camss/camss-vfe-4-7.c VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(wm)); wm 416 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_wm_set_framedrop_period(struct vfe_device *vfe, u8 wm, u8 per) wm 421 drivers/media/platform/qcom/camss/camss-vfe-4-7.c VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); wm 429 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(wm)); wm 432 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_wm_set_framedrop_pattern(struct vfe_device *vfe, u8 wm, wm 436 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_FRAMEDROP_PATTERN(wm)); wm 439 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_wm_set_ub_cfg(struct vfe_device *vfe, u8 wm, wm 446 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(reg, vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(wm)); wm 449 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_bus_reload_wm(struct vfe_device *vfe, u8 wm) wm 452 drivers/media/platform/qcom/camss/camss-vfe-4-7.c writel_relaxed(VFE_0_BUS_CMD_Mx_RLD_CMD(wm), vfe->base + VFE_0_BUS_CMD); wm 456 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_wm_set_ping_addr(struct vfe_device *vfe, u8 wm, u32 addr) wm 459 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(wm)); wm 462 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_wm_set_pong_addr(struct vfe_device *vfe, u8 wm, u32 addr) wm 465 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe->base + VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(wm)); wm 468 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static int vfe_wm_get_ping_pong_status(struct vfe_device *vfe, u8 wm) wm 474 drivers/media/platform/qcom/camss/camss-vfe-4-7.c return (reg >> wm) & 0x1; wm 485 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_bus_connect_wm_to_rdi(struct vfe_device *vfe, u8 wm, wm 514 drivers/media/platform/qcom/camss/camss-vfe-4-7.c if (wm % 2 == 1) wm 517 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_set(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); wm 520 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_wm_set_subsample(struct vfe_device *vfe, u8 wm) wm 524 drivers/media/platform/qcom/camss/camss-vfe-4-7.c VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN(wm)); wm 527 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_bus_disconnect_wm_from_rdi(struct vfe_device *vfe, u8 wm, wm 551 drivers/media/platform/qcom/camss/camss-vfe-4-7.c if (wm % 2 == 1) wm 554 drivers/media/platform/qcom/camss/camss-vfe-4-7.c vfe_reg_clr(vfe, VFE_0_BUS_XBAR_CFG_x(wm), reg); wm 677 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_enable_irq_wm_line(struct vfe_device *vfe, u8 wm, wm 680 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 irq_en0 = VFE_0_IRQ_MASK_0_IMAGE_MASTER_n_PING_PONG(wm) | wm 682 drivers/media/platform/qcom/camss/camss-vfe-4-7.c u32 irq_en1 = VFE_0_IRQ_MASK_1_IMAGE_MASTER_n_BUS_OVERFLOW(wm) | wm 925 drivers/media/platform/qcom/camss/camss-vfe-4-7.c static void vfe_set_cgc_override(struct vfe_device *vfe, u8 wm, u8 enable) wm 422 drivers/media/platform/qcom/camss/camss-vfe.c static int vfe_release_wm(struct vfe_device *vfe, u8 wm) wm 424 drivers/media/platform/qcom/camss/camss-vfe.c if (wm >= ARRAY_SIZE(vfe->wm_output_map)) wm 427 drivers/media/platform/qcom/camss/camss-vfe.c vfe->wm_output_map[wm] = VFE_LINE_NONE; wm 1006 drivers/media/platform/qcom/camss/camss-vfe.c static void vfe_isr_wm_done(struct vfe_device *vfe, u8 wm) wm 1016 drivers/media/platform/qcom/camss/camss-vfe.c active_index = vfe->ops->wm_get_ping_pong_status(vfe, wm); wm 1020 drivers/media/platform/qcom/camss/camss-vfe.c if (vfe->wm_output_map[wm] == VFE_LINE_NONE) { wm 1025 drivers/media/platform/qcom/camss/camss-vfe.c output = &vfe->line[vfe->wm_output_map[wm]].output; wm 86 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_enable)(struct vfe_device *vfe, u8 wm, u8 enable); wm 87 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_frame_based)(struct vfe_device *vfe, u8 wm, u8 enable); wm 88 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_line_based)(struct vfe_device *vfe, u32 wm, wm 91 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_set_framedrop_period)(struct vfe_device *vfe, u8 wm, u8 per); wm 92 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_set_framedrop_pattern)(struct vfe_device *vfe, u8 wm, wm 94 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_set_ub_cfg)(struct vfe_device *vfe, u8 wm, u16 offset, wm 96 drivers/media/platform/qcom/camss/camss-vfe.h void (*bus_reload_wm)(struct vfe_device *vfe, u8 wm); wm 97 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_set_ping_addr)(struct vfe_device *vfe, u8 wm, u32 addr); wm 98 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_set_pong_addr)(struct vfe_device *vfe, u8 wm, u32 addr); wm 99 drivers/media/platform/qcom/camss/camss-vfe.h int (*wm_get_ping_pong_status)(struct vfe_device *vfe, u8 wm); wm 101 drivers/media/platform/qcom/camss/camss-vfe.h void (*bus_connect_wm_to_rdi)(struct vfe_device *vfe, u8 wm, wm 103 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_set_subsample)(struct vfe_device *vfe, u8 wm); wm 104 drivers/media/platform/qcom/camss/camss-vfe.h void (*bus_disconnect_wm_from_rdi)(struct vfe_device *vfe, u8 wm, wm 115 drivers/media/platform/qcom/camss/camss-vfe.h void (*enable_irq_wm_line)(struct vfe_device *vfe, u8 wm, wm 126 drivers/media/platform/qcom/camss/camss-vfe.h void (*set_cgc_override)(struct vfe_device *vfe, u8 wm, u8 enable); wm 142 drivers/media/platform/qcom/camss/camss-vfe.h void (*wm_done)(struct vfe_device *vfe, u8 wm); wm 796 drivers/media/platform/qcom/venus/helpers.c struct hfi_video_work_mode wm; wm 801 drivers/media/platform/qcom/venus/helpers.c wm.video_work_mode = mode; wm 803 drivers/media/platform/qcom/venus/helpers.c return hfi_session_set_property(inst, ptype, &wm); wm 1194 drivers/media/platform/qcom/venus/hfi_cmds.c struct hfi_video_work_mode *in = pdata, *wm = prop_data; wm 1196 drivers/media/platform/qcom/venus/hfi_cmds.c wm->video_work_mode = in->video_work_mode; wm 1197 drivers/media/platform/qcom/venus/hfi_cmds.c pkt->shdr.hdr.size += sizeof(u32) + sizeof(*wm); wm 122 drivers/parport/parport_gsc.h const unsigned char wm = (PARPORT_CONTROL_STROBE | wm 134 drivers/parport/parport_gsc.h __parport_gsc_frob_control (p, wm, d & wm); wm 151 drivers/parport/parport_gsc.h const unsigned char wm = (PARPORT_CONTROL_STROBE | wm 168 drivers/parport/parport_gsc.h mask &= wm; wm 169 drivers/parport/parport_gsc.h val &= wm; wm 952 drivers/parport/parport_ip32.c const unsigned int wm = wm 954 drivers/parport/parport_ip32.c CHECK_EXTRA_BITS(p, c, wm); wm 955 drivers/parport/parport_ip32.c __parport_ip32_frob_control(p, wm, c & wm); wm 971 drivers/parport/parport_ip32.c const unsigned int wm = wm 973 drivers/parport/parport_ip32.c CHECK_EXTRA_BITS(p, mask, wm); wm 974 drivers/parport/parport_ip32.c CHECK_EXTRA_BITS(p, val, wm); wm 975 drivers/parport/parport_ip32.c __parport_ip32_frob_control(p, mask & wm, val & wm); wm 183 drivers/parport/parport_sunbpp.c const unsigned char wm = (PARPORT_CONTROL_STROBE | wm 188 drivers/parport/parport_sunbpp.c parport_sunbpp_frob_control (p, wm, d & wm); wm 219 drivers/video/fbdev/i740fb.c u32 wm; wm 224 drivers/video/fbdev/i740fb.c wm = 0x18120000; wm 226 drivers/video/fbdev/i740fb.c wm = 0x16110000; wm 228 drivers/video/fbdev/i740fb.c wm = 0x120E0000; wm 230 drivers/video/fbdev/i740fb.c wm = 0x100D0000; wm 236 drivers/video/fbdev/i740fb.c wm = 0x2C1D0000; wm 238 drivers/video/fbdev/i740fb.c wm = 0x2C180000; wm 240 drivers/video/fbdev/i740fb.c wm = 0x24160000; wm 242 drivers/video/fbdev/i740fb.c wm = 0x18120000; wm 244 drivers/video/fbdev/i740fb.c wm = 0x16110000; wm 246 drivers/video/fbdev/i740fb.c wm = 0x13100000; wm 248 drivers/video/fbdev/i740fb.c wm = 0x120E0000; wm 251 drivers/video/fbdev/i740fb.c wm = 0x28200000; wm 253 drivers/video/fbdev/i740fb.c wm = 0x2A1E0000; wm 255 drivers/video/fbdev/i740fb.c wm = 0x2B1A0000; wm 257 drivers/video/fbdev/i740fb.c wm = 0x2C180000; wm 259 drivers/video/fbdev/i740fb.c wm = 0x24180000; wm 261 drivers/video/fbdev/i740fb.c wm = 0x18120000; wm 263 drivers/video/fbdev/i740fb.c wm = 0x16110000; wm 265 drivers/video/fbdev/i740fb.c wm = 0x13100000; wm 267 drivers/video/fbdev/i740fb.c wm = 0x120E0000; wm 273 drivers/video/fbdev/i740fb.c wm = 0x31200000; wm 275 drivers/video/fbdev/i740fb.c wm = 0x2E200000; wm 277 drivers/video/fbdev/i740fb.c wm = 0x2C1D0000; wm 279 drivers/video/fbdev/i740fb.c wm = 0x25180000; wm 281 drivers/video/fbdev/i740fb.c wm = 0x24160000; wm 283 drivers/video/fbdev/i740fb.c wm = 0x18120000; wm 285 drivers/video/fbdev/i740fb.c wm = 0x16110000; wm 287 drivers/video/fbdev/i740fb.c wm = 0x13100000; wm 290 drivers/video/fbdev/i740fb.c wm = 0x311F0000; wm 292 drivers/video/fbdev/i740fb.c wm = 0x2C1D0000; wm 294 drivers/video/fbdev/i740fb.c wm = 0x25180000; wm 296 drivers/video/fbdev/i740fb.c wm = 0x24160000; wm 298 drivers/video/fbdev/i740fb.c wm = 0x18120000; wm 300 drivers/video/fbdev/i740fb.c wm = 0x16110000; wm 302 drivers/video/fbdev/i740fb.c wm = 0x13100000; wm 308 drivers/video/fbdev/i740fb.c wm = 0x2A200000; wm 310 drivers/video/fbdev/i740fb.c wm = 0x281A0000; wm 312 drivers/video/fbdev/i740fb.c wm = 0x25180000; wm 314 drivers/video/fbdev/i740fb.c wm = 0x18120000; wm 316 drivers/video/fbdev/i740fb.c wm = 0x16110000; wm 319 drivers/video/fbdev/i740fb.c wm = 0x29200000; wm 321 drivers/video/fbdev/i740fb.c wm = 0x281A0000; wm 323 drivers/video/fbdev/i740fb.c wm = 0x25180000; wm 325 drivers/video/fbdev/i740fb.c wm = 0x18120000; wm 327 drivers/video/fbdev/i740fb.c wm = 0x16110000; wm 332 drivers/video/fbdev/i740fb.c return wm; wm 27 drivers/video/fbdev/i810/i810_gtf.c u32 wm; wm 270 drivers/video/fbdev/i810/i810_gtf.c wm_best = wmark[i].wm; wm 159 include/linux/parport_pc.h const unsigned char wm = (PARPORT_CONTROL_STROBE | wm 171 include/linux/parport_pc.h __parport_pc_frob_control (p, wm, d & wm); wm 188 include/linux/parport_pc.h const unsigned char wm = (PARPORT_CONTROL_STROBE | wm 205 include/linux/parport_pc.h mask &= wm; wm 206 include/linux/parport_pc.h val &= wm; wm 316 include/linux/wm97xx.h enum wm97xx_gpio_status wm97xx_get_gpio(struct wm97xx *wm, u32 gpio); wm 317 include/linux/wm97xx.h void wm97xx_set_gpio(struct wm97xx *wm, u32 gpio, wm 319 include/linux/wm97xx.h void wm97xx_config_gpio(struct wm97xx *wm, u32 gpio, wm 325 include/linux/wm97xx.h void wm97xx_set_suspend_mode(struct wm97xx *wm, u16 mode); wm 328 include/linux/wm97xx.h int wm97xx_reg_read(struct wm97xx *wm, u16 reg); wm 329 include/linux/wm97xx.h void wm97xx_reg_write(struct wm97xx *wm, u16 reg, u16 val); wm 332 include/linux/wm97xx.h int wm97xx_read_aux_adc(struct wm97xx *wm, u16 adcsel); wm 70 sound/pci/ice1712/maya44.c struct snd_wm8776 wm[2]; wm 76 sound/pci/ice1712/maya44.c static void wm8776_write(struct snd_ice1712 *ice, struct snd_wm8776 *wm, wm 83 sound/pci/ice1712/maya44.c snd_vt1724_write_i2c(ice, wm->addr, wm 86 sound/pci/ice1712/maya44.c wm->regs[reg] = val; wm 92 sound/pci/ice1712/maya44.c static int wm8776_write_bits(struct snd_ice1712 *ice, struct snd_wm8776 *wm, wm 96 sound/pci/ice1712/maya44.c val |= wm->regs[reg] & ~mask; wm 97 sound/pci/ice1712/maya44.c if (val != wm->regs[reg]) { wm 98 sound/pci/ice1712/maya44.c wm8776_write(ice, wm, reg, val); wm 174 sound/pci/ice1712/maya44.c struct snd_wm8776 *wm = wm 175 sound/pci/ice1712/maya44.c &chip->wm[snd_ctl_get_ioff(kcontrol, &ucontrol->id)]; wm 179 sound/pci/ice1712/maya44.c ucontrol->value.integer.value[0] = wm->volumes[idx][0]; wm 180 sound/pci/ice1712/maya44.c ucontrol->value.integer.value[1] = wm->volumes[idx][1]; wm 189 sound/pci/ice1712/maya44.c struct snd_wm8776 *wm = wm 190 sound/pci/ice1712/maya44.c &chip->wm[snd_ctl_get_ioff(kcontrol, &ucontrol->id)]; wm 201 sound/pci/ice1712/maya44.c if (val == wm->volumes[idx][ch]) wm 208 sound/pci/ice1712/maya44.c changed |= wm8776_write_bits(chip->ice, wm, vol->regs[ch], wm 211 sound/pci/ice1712/maya44.c wm8776_write_bits(chip->ice, wm, WM8776_REG_ADC_MUX, wm 214 sound/pci/ice1712/maya44.c wm->volumes[idx][ch] = val; wm 235 sound/pci/ice1712/maya44.c struct snd_wm8776 *wm = wm 236 sound/pci/ice1712/maya44.c &chip->wm[snd_ctl_get_ioff(kcontrol, &ucontrol->id)]; wm 239 sound/pci/ice1712/maya44.c ucontrol->value.integer.value[0] = (wm->switch_bits >> idx) & 1; wm 247 sound/pci/ice1712/maya44.c struct snd_wm8776 *wm = wm 248 sound/pci/ice1712/maya44.c &chip->wm[snd_ctl_get_ioff(kcontrol, &ucontrol->id)]; wm 255 sound/pci/ice1712/maya44.c wm->switch_bits &= ~mask; wm 258 sound/pci/ice1712/maya44.c wm->switch_bits |= mask; wm 260 sound/pci/ice1712/maya44.c changed = wm8776_write_bits(chip->ice, wm, wm 339 sound/pci/ice1712/maya44.c wm8776_write_bits(chip->ice, &chip->wm[idx], WM8776_REG_ADC_MUX, wm 535 sound/pci/ice1712/maya44.c struct snd_wm8776 *wm, unsigned int addr) wm 567 sound/pci/ice1712/maya44.c wm->addr = addr; wm 569 sound/pci/ice1712/maya44.c wm->switch_bits = (1 << WM_SW_DAC); wm 575 sound/pci/ice1712/maya44.c wm8776_write(ice, wm, reg, data); wm 640 sound/pci/ice1712/maya44.c wm8776_write_bits(ice, &chip->wm[i], wm 690 sound/pci/ice1712/maya44.c wm8776_init(ice, &chip->wm[i], wm8776_addr[i]); wm 104 sound/pci/ice1712/psc724.c static void psc724_wm8766_write(struct snd_wm8766 *wm, u16 addr, u16 data) wm 106 sound/pci/ice1712/psc724.c struct psc724_spec *spec = container_of(wm, struct psc724_spec, wm8766); wm 146 sound/pci/ice1712/psc724.c static void psc724_wm8776_write(struct snd_wm8776 *wm, u8 addr, u8 data) wm 148 sound/pci/ice1712/psc724.c struct psc724_spec *spec = container_of(wm, struct psc724_spec, wm8776); wm 18 sound/pci/ice1712/wm8766.c static void snd_wm8766_write(struct snd_wm8766 *wm, u16 addr, u16 data) wm 21 sound/pci/ice1712/wm8766.c wm->regs[addr] = data; wm 22 sound/pci/ice1712/wm8766.c wm->ops.write(wm, addr, data); wm 137 sound/pci/ice1712/wm8766.c void snd_wm8766_init(struct snd_wm8766 *wm) wm 147 sound/pci/ice1712/wm8766.c memcpy(wm->ctl, snd_wm8766_default_ctl, sizeof(wm->ctl)); wm 149 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, WM8766_REG_RESET, 0x00); /* reset */ wm 153 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, i, default_values[i]); wm 156 sound/pci/ice1712/wm8766.c void snd_wm8766_resume(struct snd_wm8766 *wm) wm 161 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, i, wm->regs[i]); wm 164 sound/pci/ice1712/wm8766.c void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac) wm 166 sound/pci/ice1712/wm8766.c u16 val = wm->regs[WM8766_REG_IFCTRL] & ~WM8766_IF_MASK; wm 169 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, WM8766_REG_IFCTRL, val | dac); wm 172 sound/pci/ice1712/wm8766.c void snd_wm8766_volume_restore(struct snd_wm8766 *wm) wm 174 sound/pci/ice1712/wm8766.c u16 val = wm->regs[WM8766_REG_DACR1]; wm 176 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, WM8766_REG_DACR1, val | WM8766_VOL_UPDATE); wm 184 sound/pci/ice1712/wm8766.c struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol); wm 188 sound/pci/ice1712/wm8766.c uinfo->count = (wm->ctl[n].flags & WM8766_FLAG_STEREO) ? 2 : 1; wm 189 sound/pci/ice1712/wm8766.c uinfo->value.integer.min = wm->ctl[n].min; wm 190 sound/pci/ice1712/wm8766.c uinfo->value.integer.max = wm->ctl[n].max; wm 198 sound/pci/ice1712/wm8766.c struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol); wm 201 sound/pci/ice1712/wm8766.c return snd_ctl_enum_info(uinfo, 1, wm->ctl[n].max, wm 202 sound/pci/ice1712/wm8766.c wm->ctl[n].enum_names); wm 208 sound/pci/ice1712/wm8766.c struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol); wm 212 sound/pci/ice1712/wm8766.c if (wm->ctl[n].get) wm 213 sound/pci/ice1712/wm8766.c wm->ctl[n].get(wm, &val1, &val2); wm 215 sound/pci/ice1712/wm8766.c val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; wm 216 sound/pci/ice1712/wm8766.c val1 >>= __ffs(wm->ctl[n].mask1); wm 217 sound/pci/ice1712/wm8766.c if (wm->ctl[n].flags & WM8766_FLAG_STEREO) { wm 218 sound/pci/ice1712/wm8766.c val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; wm 219 sound/pci/ice1712/wm8766.c val2 >>= __ffs(wm->ctl[n].mask2); wm 220 sound/pci/ice1712/wm8766.c if (wm->ctl[n].flags & WM8766_FLAG_VOL_UPDATE) wm 224 sound/pci/ice1712/wm8766.c if (wm->ctl[n].flags & WM8766_FLAG_INVERT) { wm 225 sound/pci/ice1712/wm8766.c val1 = wm->ctl[n].max - (val1 - wm->ctl[n].min); wm 226 sound/pci/ice1712/wm8766.c if (wm->ctl[n].flags & WM8766_FLAG_STEREO) wm 227 sound/pci/ice1712/wm8766.c val2 = wm->ctl[n].max - (val2 - wm->ctl[n].min); wm 230 sound/pci/ice1712/wm8766.c if (wm->ctl[n].flags & WM8766_FLAG_STEREO) wm 239 sound/pci/ice1712/wm8766.c struct snd_wm8766 *wm = snd_kcontrol_chip(kcontrol); wm 246 sound/pci/ice1712/wm8766.c if (wm->ctl[n].flags & WM8766_FLAG_INVERT) { wm 247 sound/pci/ice1712/wm8766.c regval1 = wm->ctl[n].max - (regval1 - wm->ctl[n].min); wm 248 sound/pci/ice1712/wm8766.c regval2 = wm->ctl[n].max - (regval2 - wm->ctl[n].min); wm 250 sound/pci/ice1712/wm8766.c if (wm->ctl[n].set) wm 251 sound/pci/ice1712/wm8766.c wm->ctl[n].set(wm, regval1, regval2); wm 253 sound/pci/ice1712/wm8766.c val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; wm 254 sound/pci/ice1712/wm8766.c val |= regval1 << __ffs(wm->ctl[n].mask1); wm 256 sound/pci/ice1712/wm8766.c if (wm->ctl[n].flags & WM8766_FLAG_STEREO && wm 257 sound/pci/ice1712/wm8766.c wm->ctl[n].reg1 == wm->ctl[n].reg2) { wm 258 sound/pci/ice1712/wm8766.c val &= ~wm->ctl[n].mask2; wm 259 sound/pci/ice1712/wm8766.c val |= regval2 << __ffs(wm->ctl[n].mask2); wm 261 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, wm->ctl[n].reg1, val); wm 263 sound/pci/ice1712/wm8766.c if (wm->ctl[n].flags & WM8766_FLAG_STEREO && wm 264 sound/pci/ice1712/wm8766.c wm->ctl[n].reg1 != wm->ctl[n].reg2) { wm 265 sound/pci/ice1712/wm8766.c val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; wm 266 sound/pci/ice1712/wm8766.c val |= regval2 << __ffs(wm->ctl[n].mask2); wm 267 sound/pci/ice1712/wm8766.c if (wm->ctl[n].flags & WM8766_FLAG_VOL_UPDATE) wm 269 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, wm->ctl[n].reg2, val); wm 276 sound/pci/ice1712/wm8766.c static int snd_wm8766_add_control(struct snd_wm8766 *wm, int num) wm 284 sound/pci/ice1712/wm8766.c cont.name = wm->ctl[num].name; wm 286 sound/pci/ice1712/wm8766.c if (wm->ctl[num].flags & WM8766_FLAG_LIM || wm 287 sound/pci/ice1712/wm8766.c wm->ctl[num].flags & WM8766_FLAG_ALC) wm 293 sound/pci/ice1712/wm8766.c switch (wm->ctl[num].type) { wm 297 sound/pci/ice1712/wm8766.c cont.tlv.p = wm->ctl[num].tlv; wm 300 sound/pci/ice1712/wm8766.c wm->ctl[num].max = 1; wm 301 sound/pci/ice1712/wm8766.c if (wm->ctl[num].flags & WM8766_FLAG_STEREO) wm 312 sound/pci/ice1712/wm8766.c ctl = snd_ctl_new1(&cont, wm); wm 315 sound/pci/ice1712/wm8766.c wm->ctl[num].kctl = ctl; wm 317 sound/pci/ice1712/wm8766.c return snd_ctl_add(wm->card, ctl); wm 320 sound/pci/ice1712/wm8766.c int snd_wm8766_build_controls(struct snd_wm8766 *wm) wm 325 sound/pci/ice1712/wm8766.c if (wm->ctl[i].name) { wm 326 sound/pci/ice1712/wm8766.c err = snd_wm8766_add_control(wm, i); wm 88 sound/pci/ice1712/wm8766.h void (*write)(struct snd_wm8766 *wm, u16 addr, u16 data); wm 125 sound/pci/ice1712/wm8766.h void (*set)(struct snd_wm8766 *wm, u16 ch1, u16 ch2); wm 126 sound/pci/ice1712/wm8766.h void (*get)(struct snd_wm8766 *wm, u16 *ch1, u16 *ch2); wm 141 sound/pci/ice1712/wm8766.h void snd_wm8766_init(struct snd_wm8766 *wm); wm 142 sound/pci/ice1712/wm8766.h void snd_wm8766_resume(struct snd_wm8766 *wm); wm 143 sound/pci/ice1712/wm8766.h void snd_wm8766_set_if(struct snd_wm8766 *wm, u16 dac); wm 144 sound/pci/ice1712/wm8766.h void snd_wm8766_volume_restore(struct snd_wm8766 *wm); wm 145 sound/pci/ice1712/wm8766.h int snd_wm8766_build_controls(struct snd_wm8766 *wm); wm 18 sound/pci/ice1712/wm8776.c static void snd_wm8776_write(struct snd_wm8776 *wm, u16 addr, u16 data) wm 24 sound/pci/ice1712/wm8776.c wm->regs[addr] = data; wm 25 sound/pci/ice1712/wm8776.c wm->ops.write(wm, bus_addr, bus_data); wm 30 sound/pci/ice1712/wm8776.c static void snd_wm8776_activate_ctl(struct snd_wm8776 *wm, wm 34 sound/pci/ice1712/wm8776.c struct snd_card *card = wm->card; wm 55 sound/pci/ice1712/wm8776.c static void snd_wm8776_update_agc_ctl(struct snd_wm8776 *wm) wm 59 sound/pci/ice1712/wm8776.c switch (wm->agc_mode) { wm 76 sound/pci/ice1712/wm8776.c if (wm->ctl[i].flags & flags_off) wm 77 sound/pci/ice1712/wm8776.c snd_wm8776_activate_ctl(wm, wm->ctl[i].name, false); wm 78 sound/pci/ice1712/wm8776.c else if (wm->ctl[i].flags & flags_on) wm 79 sound/pci/ice1712/wm8776.c snd_wm8776_activate_ctl(wm, wm->ctl[i].name, true); wm 82 sound/pci/ice1712/wm8776.c static void snd_wm8776_set_agc(struct snd_wm8776 *wm, u16 agc, u16 nothing) wm 84 sound/pci/ice1712/wm8776.c u16 alc1 = wm->regs[WM8776_REG_ALCCTRL1] & ~WM8776_ALC1_LCT_MASK; wm 85 sound/pci/ice1712/wm8776.c u16 alc2 = wm->regs[WM8776_REG_ALCCTRL2] & ~WM8776_ALC2_LCEN; wm 89 sound/pci/ice1712/wm8776.c wm->agc_mode = WM8776_AGC_OFF; wm 93 sound/pci/ice1712/wm8776.c wm->agc_mode = WM8776_AGC_LIM; wm 98 sound/pci/ice1712/wm8776.c wm->agc_mode = WM8776_AGC_ALC_R; wm 103 sound/pci/ice1712/wm8776.c wm->agc_mode = WM8776_AGC_ALC_L; wm 108 sound/pci/ice1712/wm8776.c wm->agc_mode = WM8776_AGC_ALC_STEREO; wm 111 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, WM8776_REG_ALCCTRL1, alc1); wm 112 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, WM8776_REG_ALCCTRL2, alc2); wm 113 sound/pci/ice1712/wm8776.c snd_wm8776_update_agc_ctl(wm); wm 116 sound/pci/ice1712/wm8776.c static void snd_wm8776_get_agc(struct snd_wm8776 *wm, u16 *mode, u16 *nothing) wm 118 sound/pci/ice1712/wm8776.c *mode = wm->agc_mode; wm 412 sound/pci/ice1712/wm8776.c void snd_wm8776_init(struct snd_wm8776 *wm) wm 424 sound/pci/ice1712/wm8776.c memcpy(wm->ctl, snd_wm8776_default_ctl, sizeof(wm->ctl)); wm 426 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, WM8776_REG_RESET, 0x00); /* reset */ wm 430 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, i, default_values[i]); wm 433 sound/pci/ice1712/wm8776.c void snd_wm8776_resume(struct snd_wm8776 *wm) wm 438 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, i, wm->regs[i]); wm 441 sound/pci/ice1712/wm8776.c void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power) wm 443 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, WM8776_REG_PWRDOWN, power); wm 446 sound/pci/ice1712/wm8776.c void snd_wm8776_volume_restore(struct snd_wm8776 *wm) wm 448 sound/pci/ice1712/wm8776.c u16 val = wm->regs[WM8776_REG_DACRVOL]; wm 450 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, WM8776_REG_DACRVOL, val | WM8776_VOL_UPDATE); wm 458 sound/pci/ice1712/wm8776.c struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol); wm 462 sound/pci/ice1712/wm8776.c uinfo->count = (wm->ctl[n].flags & WM8776_FLAG_STEREO) ? 2 : 1; wm 463 sound/pci/ice1712/wm8776.c uinfo->value.integer.min = wm->ctl[n].min; wm 464 sound/pci/ice1712/wm8776.c uinfo->value.integer.max = wm->ctl[n].max; wm 472 sound/pci/ice1712/wm8776.c struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol); wm 475 sound/pci/ice1712/wm8776.c return snd_ctl_enum_info(uinfo, 1, wm->ctl[n].max, wm 476 sound/pci/ice1712/wm8776.c wm->ctl[n].enum_names); wm 482 sound/pci/ice1712/wm8776.c struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol); wm 486 sound/pci/ice1712/wm8776.c if (wm->ctl[n].get) wm 487 sound/pci/ice1712/wm8776.c wm->ctl[n].get(wm, &val1, &val2); wm 489 sound/pci/ice1712/wm8776.c val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; wm 490 sound/pci/ice1712/wm8776.c val1 >>= __ffs(wm->ctl[n].mask1); wm 491 sound/pci/ice1712/wm8776.c if (wm->ctl[n].flags & WM8776_FLAG_STEREO) { wm 492 sound/pci/ice1712/wm8776.c val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; wm 493 sound/pci/ice1712/wm8776.c val2 >>= __ffs(wm->ctl[n].mask2); wm 494 sound/pci/ice1712/wm8776.c if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE) wm 498 sound/pci/ice1712/wm8776.c if (wm->ctl[n].flags & WM8776_FLAG_INVERT) { wm 499 sound/pci/ice1712/wm8776.c val1 = wm->ctl[n].max - (val1 - wm->ctl[n].min); wm 500 sound/pci/ice1712/wm8776.c if (wm->ctl[n].flags & WM8776_FLAG_STEREO) wm 501 sound/pci/ice1712/wm8776.c val2 = wm->ctl[n].max - (val2 - wm->ctl[n].min); wm 504 sound/pci/ice1712/wm8776.c if (wm->ctl[n].flags & WM8776_FLAG_STEREO) wm 513 sound/pci/ice1712/wm8776.c struct snd_wm8776 *wm = snd_kcontrol_chip(kcontrol); wm 520 sound/pci/ice1712/wm8776.c if (wm->ctl[n].flags & WM8776_FLAG_INVERT) { wm 521 sound/pci/ice1712/wm8776.c regval1 = wm->ctl[n].max - (regval1 - wm->ctl[n].min); wm 522 sound/pci/ice1712/wm8776.c regval2 = wm->ctl[n].max - (regval2 - wm->ctl[n].min); wm 524 sound/pci/ice1712/wm8776.c if (wm->ctl[n].set) wm 525 sound/pci/ice1712/wm8776.c wm->ctl[n].set(wm, regval1, regval2); wm 527 sound/pci/ice1712/wm8776.c val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; wm 528 sound/pci/ice1712/wm8776.c val |= regval1 << __ffs(wm->ctl[n].mask1); wm 530 sound/pci/ice1712/wm8776.c if (wm->ctl[n].flags & WM8776_FLAG_STEREO && wm 531 sound/pci/ice1712/wm8776.c wm->ctl[n].reg1 == wm->ctl[n].reg2) { wm 532 sound/pci/ice1712/wm8776.c val &= ~wm->ctl[n].mask2; wm 533 sound/pci/ice1712/wm8776.c val |= regval2 << __ffs(wm->ctl[n].mask2); wm 535 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, wm->ctl[n].reg1, val); wm 537 sound/pci/ice1712/wm8776.c if (wm->ctl[n].flags & WM8776_FLAG_STEREO && wm 538 sound/pci/ice1712/wm8776.c wm->ctl[n].reg1 != wm->ctl[n].reg2) { wm 539 sound/pci/ice1712/wm8776.c val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; wm 540 sound/pci/ice1712/wm8776.c val |= regval2 << __ffs(wm->ctl[n].mask2); wm 541 sound/pci/ice1712/wm8776.c if (wm->ctl[n].flags & WM8776_FLAG_VOL_UPDATE) wm 543 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, wm->ctl[n].reg2, val); wm 550 sound/pci/ice1712/wm8776.c static int snd_wm8776_add_control(struct snd_wm8776 *wm, int num) wm 558 sound/pci/ice1712/wm8776.c cont.name = wm->ctl[num].name; wm 560 sound/pci/ice1712/wm8776.c if (wm->ctl[num].flags & WM8776_FLAG_LIM || wm 561 sound/pci/ice1712/wm8776.c wm->ctl[num].flags & WM8776_FLAG_ALC) wm 567 sound/pci/ice1712/wm8776.c switch (wm->ctl[num].type) { wm 571 sound/pci/ice1712/wm8776.c cont.tlv.p = wm->ctl[num].tlv; wm 574 sound/pci/ice1712/wm8776.c wm->ctl[num].max = 1; wm 575 sound/pci/ice1712/wm8776.c if (wm->ctl[num].flags & WM8776_FLAG_STEREO) wm 586 sound/pci/ice1712/wm8776.c ctl = snd_ctl_new1(&cont, wm); wm 590 sound/pci/ice1712/wm8776.c return snd_ctl_add(wm->card, ctl); wm 593 sound/pci/ice1712/wm8776.c int snd_wm8776_build_controls(struct snd_wm8776 *wm) wm 598 sound/pci/ice1712/wm8776.c if (wm->ctl[i].name) { wm 599 sound/pci/ice1712/wm8776.c err = snd_wm8776_add_control(wm, i); wm 127 sound/pci/ice1712/wm8776.h void (*write)(struct snd_wm8776 *wm, u8 addr, u8 data); wm 181 sound/pci/ice1712/wm8776.h void (*set)(struct snd_wm8776 *wm, u16 ch1, u16 ch2); wm 182 sound/pci/ice1712/wm8776.h void (*get)(struct snd_wm8776 *wm, u16 *ch1, u16 *ch2); wm 203 sound/pci/ice1712/wm8776.h void snd_wm8776_init(struct snd_wm8776 *wm); wm 204 sound/pci/ice1712/wm8776.h void snd_wm8776_resume(struct snd_wm8776 *wm); wm 205 sound/pci/ice1712/wm8776.h void snd_wm8776_set_power(struct snd_wm8776 *wm, u16 power); wm 206 sound/pci/ice1712/wm8776.h void snd_wm8776_volume_restore(struct snd_wm8776 *wm); wm 207 sound/pci/ice1712/wm8776.h int snd_wm8776_build_controls(struct snd_wm8776 *wm); wm 1242 sound/soc/fsl/fsl_ssi.c u32 wm = ssi->fifo_watermark; wm 1249 sound/soc/fsl/fsl_ssi.c SSI_SFCSR_TFWM0(wm) | SSI_SFCSR_RFWM0(wm) | wm 1250 sound/soc/fsl/fsl_ssi.c SSI_SFCSR_TFWM1(wm) | SSI_SFCSR_RFWM1(wm));