win_enable        410 arch/arm/mach-orion5x/pci.c 	u32 win_enable;
win_enable        417 arch/arm/mach-orion5x/pci.c 	win_enable = 0xffffffff;
win_enable        418 arch/arm/mach-orion5x/pci.c 	writel(win_enable, PCI_BAR_ENABLE);
win_enable        452 arch/arm/mach-orion5x/pci.c 		win_enable &= ~(1 << cs->cs_index);
win_enable        458 arch/arm/mach-orion5x/pci.c 	writel(win_enable, PCI_BAR_ENABLE);
win_enable        487 drivers/dma/mv_xor.c 	u32 win_enable;
win_enable        531 drivers/dma/mv_xor.c 	win_enable = readl(base + WINDOW_BAR_ENABLE(0));
win_enable        534 drivers/dma/mv_xor.c 	i = ffs(~win_enable) - 1;
win_enable        546 drivers/dma/mv_xor.c 	win_enable |= (1 << i);
win_enable        547 drivers/dma/mv_xor.c 	win_enable |= 3 << (16 + (2 * i));
win_enable        548 drivers/dma/mv_xor.c 	writel(win_enable, base + WINDOW_BAR_ENABLE(0));
win_enable        549 drivers/dma/mv_xor.c 	writel(win_enable, base + WINDOW_BAR_ENABLE(1));
win_enable       1167 drivers/dma/mv_xor.c 	u32 win_enable = 0;
win_enable       1189 drivers/dma/mv_xor.c 		win_enable |= (1 << i);
win_enable       1190 drivers/dma/mv_xor.c 		win_enable |= 3 << (16 + (2 * i));
win_enable       1193 drivers/dma/mv_xor.c 	writel(win_enable, base + WINDOW_BAR_ENABLE(0));
win_enable       1194 drivers/dma/mv_xor.c 	writel(win_enable, base + WINDOW_BAR_ENABLE(1));
win_enable       1203 drivers/dma/mv_xor.c 	u32 win_enable = 0;
win_enable       1217 drivers/dma/mv_xor.c 	win_enable |= 1;
win_enable       1218 drivers/dma/mv_xor.c 	win_enable |= 3 << 16;
win_enable       1220 drivers/dma/mv_xor.c 	writel(win_enable, base + WINDOW_BAR_ENABLE(0));
win_enable       1221 drivers/dma/mv_xor.c 	writel(win_enable, base + WINDOW_BAR_ENABLE(1));
win_enable       2623 drivers/net/ethernet/marvell/mv643xx_eth.c 	u32 win_enable;
win_enable       2634 drivers/net/ethernet/marvell/mv643xx_eth.c 	win_enable = 0x3f;
win_enable       2645 drivers/net/ethernet/marvell/mv643xx_eth.c 		win_enable &= ~(1 << i);
win_enable       2649 drivers/net/ethernet/marvell/mv643xx_eth.c 	writel(win_enable, base + WINDOW_BAR_ENABLE);
win_enable        983 drivers/net/ethernet/marvell/mvneta.c 	u32 win_enable, win_protect;
win_enable        986 drivers/net/ethernet/marvell/mvneta.c 	win_enable = mvreg_read(pp, MVNETA_BASE_ADDR_ENABLE);
win_enable        991 drivers/net/ethernet/marvell/mvneta.c 			if (win_enable & (1 << i)) {
win_enable       1017 drivers/net/ethernet/marvell/mvneta.c 	win_enable &= ~(1 << i);
win_enable       1018 drivers/net/ethernet/marvell/mvneta.c 	mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
win_enable       4422 drivers/net/ethernet/marvell/mvneta.c 	u32 win_enable;
win_enable       4434 drivers/net/ethernet/marvell/mvneta.c 	win_enable = 0x3f;
win_enable       4449 drivers/net/ethernet/marvell/mvneta.c 			win_enable &= ~(1 << i);
win_enable       4458 drivers/net/ethernet/marvell/mvneta.c 		win_enable &= ~BIT(0);
win_enable       4462 drivers/net/ethernet/marvell/mvneta.c 	mvreg_write(pp, MVNETA_BASE_ADDR_ENABLE, win_enable);
win_enable       5464 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	u32 win_enable;
win_enable       5475 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	win_enable = 0;
win_enable       5487 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 		win_enable |= (1 << i);
win_enable       5490 drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c 	mvpp2_write(priv, MVPP2_BASE_ADDR_ENABLE, win_enable);