wg 223 drivers/dma/mediatek/mtk-uart-apdma.c unsigned int len, wg, rg; wg 236 drivers/dma/mediatek/mtk-uart-apdma.c wg = mtk_uart_apdma_read(c, VFF_WPT); wg 237 drivers/dma/mediatek/mtk-uart-apdma.c cnt = (wg & VFF_RING_SIZE) - (rg & VFF_RING_SIZE); wg 243 drivers/dma/mediatek/mtk-uart-apdma.c if ((rg ^ wg) & VFF_RING_WRAP) wg 247 drivers/dma/mediatek/mtk-uart-apdma.c mtk_uart_apdma_write(c, VFF_RPT, wg); wg 115 drivers/gpio/gpio-wcove.c static void wcove_update_irq_mask(struct wcove_gpio *wg, int gpio) wg 127 drivers/gpio/gpio-wcove.c if (wg->set_irq_mask) wg 128 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, mask, mask); wg 130 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, mask, 0); wg 133 drivers/gpio/gpio-wcove.c static void wcove_update_irq_ctrl(struct wcove_gpio *wg, int gpio) wg 140 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, CTLI_INTCNT_BE, wg->intcnt); wg 145 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 151 drivers/gpio/gpio-wcove.c return regmap_write(wg->regmap, reg, CTLO_INPUT_SET); wg 157 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 163 drivers/gpio/gpio-wcove.c return regmap_write(wg->regmap, reg, CTLO_OUTPUT_SET | value); wg 168 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 175 drivers/gpio/gpio-wcove.c ret = regmap_read(wg->regmap, reg, &val); wg 184 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 191 drivers/gpio/gpio-wcove.c ret = regmap_read(wg->regmap, reg, &val); wg 200 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 207 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, 1, 1); wg 209 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, reg, 1, 0); wg 215 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 223 drivers/gpio/gpio-wcove.c return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, wg 226 drivers/gpio/gpio-wcove.c return regmap_update_bits(wg->regmap, reg, CTLO_DRV_MASK, wg 238 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 245 drivers/gpio/gpio-wcove.c wg->intcnt = CTLI_INTCNT_DIS; wg 248 drivers/gpio/gpio-wcove.c wg->intcnt = CTLI_INTCNT_BE; wg 251 drivers/gpio/gpio-wcove.c wg->intcnt = CTLI_INTCNT_PE; wg 254 drivers/gpio/gpio-wcove.c wg->intcnt = CTLI_INTCNT_NE; wg 260 drivers/gpio/gpio-wcove.c wg->update |= UPDATE_IRQ_TYPE; wg 268 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 270 drivers/gpio/gpio-wcove.c mutex_lock(&wg->buslock); wg 276 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 279 drivers/gpio/gpio-wcove.c if (wg->update & UPDATE_IRQ_TYPE) wg 280 drivers/gpio/gpio-wcove.c wcove_update_irq_ctrl(wg, gpio); wg 281 drivers/gpio/gpio-wcove.c if (wg->update & UPDATE_IRQ_MASK) wg 282 drivers/gpio/gpio-wcove.c wcove_update_irq_mask(wg, gpio); wg 283 drivers/gpio/gpio-wcove.c wg->update = 0; wg 285 drivers/gpio/gpio-wcove.c mutex_unlock(&wg->buslock); wg 291 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 296 drivers/gpio/gpio-wcove.c wg->set_irq_mask = false; wg 297 drivers/gpio/gpio-wcove.c wg->update |= UPDATE_IRQ_MASK; wg 303 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 308 drivers/gpio/gpio-wcove.c wg->set_irq_mask = true; wg 309 drivers/gpio/gpio-wcove.c wg->update |= UPDATE_IRQ_MASK; wg 323 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = (struct wcove_gpio *)data; wg 327 drivers/gpio/gpio-wcove.c if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { wg 328 drivers/gpio/gpio-wcove.c dev_err(wg->dev, "Failed to read irq status register\n"); wg 344 drivers/gpio/gpio-wcove.c virq = irq_find_mapping(wg->chip.irq.domain, gpio); wg 346 drivers/gpio/gpio-wcove.c regmap_update_bits(wg->regmap, IRQ_STATUS_BASE + offset, wg 351 drivers/gpio/gpio-wcove.c if (regmap_bulk_read(wg->regmap, IRQ_STATUS_BASE, p, 2)) { wg 352 drivers/gpio/gpio-wcove.c dev_err(wg->dev, "Failed to read irq status\n"); wg 366 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg = gpiochip_get_data(chip); wg 371 drivers/gpio/gpio-wcove.c ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_OUT), &ctlo); wg 372 drivers/gpio/gpio-wcove.c ret += regmap_read(wg->regmap, to_reg(gpio, CTRL_IN), &ctli); wg 373 drivers/gpio/gpio-wcove.c ret += regmap_read(wg->regmap, IRQ_MASK_BASE + group, wg 375 drivers/gpio/gpio-wcove.c ret += regmap_read(wg->regmap, IRQ_STATUS_BASE + group, wg 397 drivers/gpio/gpio-wcove.c struct wcove_gpio *wg; wg 418 drivers/gpio/gpio-wcove.c wg = devm_kzalloc(dev, sizeof(*wg), GFP_KERNEL); wg 419 drivers/gpio/gpio-wcove.c if (!wg) wg 422 drivers/gpio/gpio-wcove.c wg->regmap_irq_chip = pmic->irq_chip_data; wg 424 drivers/gpio/gpio-wcove.c platform_set_drvdata(pdev, wg); wg 426 drivers/gpio/gpio-wcove.c mutex_init(&wg->buslock); wg 427 drivers/gpio/gpio-wcove.c wg->chip.label = KBUILD_MODNAME; wg 428 drivers/gpio/gpio-wcove.c wg->chip.direction_input = wcove_gpio_dir_in; wg 429 drivers/gpio/gpio-wcove.c wg->chip.direction_output = wcove_gpio_dir_out; wg 430 drivers/gpio/gpio-wcove.c wg->chip.get_direction = wcove_gpio_get_direction; wg 431 drivers/gpio/gpio-wcove.c wg->chip.get = wcove_gpio_get; wg 432 drivers/gpio/gpio-wcove.c wg->chip.set = wcove_gpio_set; wg 433 drivers/gpio/gpio-wcove.c wg->chip.set_config = wcove_gpio_set_config, wg 434 drivers/gpio/gpio-wcove.c wg->chip.base = -1; wg 435 drivers/gpio/gpio-wcove.c wg->chip.ngpio = WCOVE_VGPIO_NUM; wg 436 drivers/gpio/gpio-wcove.c wg->chip.can_sleep = true; wg 437 drivers/gpio/gpio-wcove.c wg->chip.parent = pdev->dev.parent; wg 438 drivers/gpio/gpio-wcove.c wg->chip.dbg_show = wcove_gpio_dbg_show; wg 439 drivers/gpio/gpio-wcove.c wg->dev = dev; wg 440 drivers/gpio/gpio-wcove.c wg->regmap = pmic->regmap; wg 442 drivers/gpio/gpio-wcove.c ret = devm_gpiochip_add_data(dev, &wg->chip, wg); wg 448 drivers/gpio/gpio-wcove.c ret = gpiochip_irqchip_add_nested(&wg->chip, &wcove_irqchip, 0, wg 455 drivers/gpio/gpio-wcove.c virq = regmap_irq_get_virq(wg->regmap_irq_chip, irq); wg 462 drivers/gpio/gpio-wcove.c wcove_gpio_irq_handler, IRQF_ONESHOT, pdev->name, wg); wg 468 drivers/gpio/gpio-wcove.c gpiochip_set_nested_irqchip(&wg->chip, &wcove_irqchip, virq); wg 471 drivers/gpio/gpio-wcove.c ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE, GPIO_IRQ0_MASK, wg 477 drivers/gpio/gpio-wcove.c ret = regmap_update_bits(wg->regmap, IRQ_MASK_BASE + 1, GPIO_IRQ1_MASK, wg 5329 drivers/md/raid5.c struct r5worker_group *wg; wg 5336 drivers/md/raid5.c wg = NULL; wg 5344 drivers/md/raid5.c wg = &conf->worker_groups[group]; wg 5350 drivers/md/raid5.c wg = &conf->worker_groups[i]; wg 5397 drivers/md/raid5.c wg = NULL; wg 5408 drivers/md/raid5.c if (wg) { wg 5409 drivers/md/raid5.c wg->stripes_cnt--; wg 78 drivers/media/platform/omap3isp/isphist.c wb_gain = conf->wg[0] << ISPHIST_WB_GAIN_WG00_SHIFT; wg 79 drivers/media/platform/omap3isp/isphist.c wb_gain |= conf->wg[1] << ISPHIST_WB_GAIN_WG01_SHIFT; wg 80 drivers/media/platform/omap3isp/isphist.c wb_gain |= conf->wg[2] << ISPHIST_WB_GAIN_WG02_SHIFT; wg 82 drivers/media/platform/omap3isp/isphist.c wb_gain |= conf->wg[3] << ISPHIST_WB_GAIN_WG03_SHIFT; wg 378 drivers/media/platform/omap3isp/isphist.c else if (cur_cfg->wg[c] != user_cfg->wg[c]) wg 248 include/uapi/linux/omap3isp.h __u8 wg[OMAP3ISP_HIST_MAX_WG]; /* White Balance Gain */