wb_layer 442 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c struct komeda_layer *wb_layer; wb_layer 447 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c c = komeda_component_add(&d71->pipes[pipe_id]->base, sizeof(*wb_layer), wb_layer 457 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c wb_layer = to_layer(c); wb_layer 458 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c wb_layer->layer_type = KOMEDA_FMT_WB_LAYER; wb_layer 460 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&wb_layer->hsize_in, D71_MIN_LINE_SIZE, d71->max_line_size); wb_layer 461 drivers/gpu/drm/arm/display/komeda/d71/d71_component.c set_range(&wb_layer->vsize_in, D71_MIN_VERTICAL_SIZE, d71->max_vsize); wb_layer 60 drivers/gpu/drm/arm/display/komeda/komeda_kms.h struct komeda_layer *wb_layer; wb_layer 80 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c pos = to_cpos(pipe->wb_layer); wb_layer 407 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h struct komeda_layer *wb_layer; wb_layer 516 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h int komeda_build_wb_data_flow(struct komeda_layer *wb_layer, wb_layer 527 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h int komeda_build_wb_split_data_flow(struct komeda_layer *wb_layer, wb_layer 382 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_wb_layer_validate(struct komeda_layer *wb_layer, wb_layer 391 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c err = komeda_layer_check_cfg(wb_layer, kfb, dflow); wb_layer 395 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c c_st = komeda_component_get_state_and_set_user(&wb_layer->base, wb_layer 410 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c komeda_component_set_output(&dflow->input, &wb_layer->base, 0); wb_layer 1082 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c int komeda_build_wb_data_flow(struct komeda_layer *wb_layer, wb_layer 1094 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c return komeda_wb_layer_validate(wb_layer, conn_st, dflow); wb_layer 1102 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c int komeda_build_wb_split_data_flow(struct komeda_layer *wb_layer, wb_layer 1107 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c struct komeda_pipeline *pipe = wb_layer->base.pipeline; wb_layer 1129 drivers/gpu/drm/arm/display/komeda/komeda_pipeline_state.c return komeda_wb_layer_validate(wb_layer, conn_st, dflow); wb_layer 385 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c if (pipe->wb_layer) { wb_layer 386 drivers/gpu/drm/arm/display/komeda/komeda_private_obj.c err = komeda_layer_obj_add(kms, pipe->wb_layer); wb_layer 11 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c komeda_wb_init_data_flow(struct komeda_layer *wb_layer, wb_layer 25 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c dflow->input.component = &wb_layer->base.pipeline->compiz->base; wb_layer 30 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c komeda_complete_data_flow_cfg(wb_layer, dflow, fb); wb_layer 42 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c struct komeda_layer *wb_layer; wb_layer 54 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c wb_layer = to_kconn(to_wb_conn(conn_st->connector))->wb_layer; wb_layer 64 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c err = komeda_wb_init_data_flow(wb_layer, conn_st, kcrtc_st, &dflow); wb_layer 69 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c err = komeda_build_wb_split_data_flow(wb_layer, wb_layer 72 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c err = komeda_build_wb_data_flow(wb_layer, wb_layer 147 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c if (!kcrtc->master->wb_layer) wb_layer 154 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c kwb_conn->wb_layer = kcrtc->master->wb_layer; wb_layer 160 drivers/gpu/drm/arm/display/komeda/komeda_wb_connector.c kwb_conn->wb_layer->layer_type,