waddr 62 arch/arm/kernel/patch.c void *waddr = addr; waddr 66 arch/arm/kernel/patch.c waddr = patch_map(addr, FIX_TEXT_POKE0, &flags); waddr 71 arch/arm/kernel/patch.c *(u16 *)waddr = __opcode_to_mem_thumb16(insn); waddr 76 arch/arm/kernel/patch.c u16 *addrh0 = waddr; waddr 77 arch/arm/kernel/patch.c u16 *addrh1 = waddr + 2; waddr 98 arch/arm/kernel/patch.c *(u32 *)waddr = insn; waddr 102 arch/arm/kernel/patch.c if (waddr != addr) { waddr 103 arch/arm/kernel/patch.c flush_kernel_vmap_range(waddr, twopage ? size / 2 : size); waddr 121 arch/arm64/kernel/insn.c void *waddr = addr; waddr 126 arch/arm64/kernel/insn.c waddr = patch_map(addr, FIX_TEXT_POKE0); waddr 128 arch/arm64/kernel/insn.c ret = probe_kernel_write(waddr, &insn, AARCH64_INSN_SIZE); waddr 101 drivers/gpu/drm/vc4/vc4_validate_shaders.c waddr_to_live_reg_index(uint32_t waddr, bool is_b) waddr 103 drivers/gpu/drm/vc4/vc4_validate_shaders.c if (waddr < 32) { waddr 105 drivers/gpu/drm/vc4/vc4_validate_shaders.c return 32 + waddr; waddr 107 drivers/gpu/drm/vc4/vc4_validate_shaders.c return waddr; waddr 108 drivers/gpu/drm/vc4/vc4_validate_shaders.c } else if (waddr <= QPU_W_ACC3) { waddr 109 drivers/gpu/drm/vc4/vc4_validate_shaders.c return 64 + waddr - QPU_W_ACC0; waddr 141 drivers/gpu/drm/vc4/vc4_validate_shaders.c is_tmu_submit(uint32_t waddr) waddr 143 drivers/gpu/drm/vc4/vc4_validate_shaders.c return (waddr == QPU_W_TMU0_S || waddr 144 drivers/gpu/drm/vc4/vc4_validate_shaders.c waddr == QPU_W_TMU1_S); waddr 148 drivers/gpu/drm/vc4/vc4_validate_shaders.c is_tmu_write(uint32_t waddr) waddr 150 drivers/gpu/drm/vc4/vc4_validate_shaders.c return (waddr >= QPU_W_TMU0_S && waddr 151 drivers/gpu/drm/vc4/vc4_validate_shaders.c waddr <= QPU_W_TMU1_B); waddr 188 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr = (is_mul ? waddr 193 drivers/gpu/drm/vc4/vc4_validate_shaders.c int tmu = waddr > QPU_W_TMU0_B; waddr 194 drivers/gpu/drm/vc4/vc4_validate_shaders.c bool submit = is_tmu_submit(waddr); waddr 391 drivers/gpu/drm/vc4/vc4_validate_shaders.c uint32_t waddr = (is_mul ? waddr 397 drivers/gpu/drm/vc4/vc4_validate_shaders.c u32 lri = waddr_to_live_reg_index(waddr, is_b); waddr 417 drivers/gpu/drm/vc4/vc4_validate_shaders.c switch (waddr) { waddr 455 drivers/gpu/drm/vc4/vc4_validate_shaders.c DRM_DEBUG("Unsupported waddr %d\n", waddr); waddr 1742 drivers/media/dvb-frontends/drx39xyj/drx_driver.h u32 waddr, /* write address of register */ waddr 1761 drivers/media/dvb-frontends/drx39xyj/drx_driver.h u32 waddr, /* write address of register */ waddr 1780 drivers/media/dvb-frontends/drx39xyj/drx_driver.h u32 waddr, /* write address of register */ waddr 540 drivers/media/dvb-frontends/drx39xyj/drxj.c u32 waddr, waddr 1763 drivers/media/dvb-frontends/drx39xyj/drxj.c u32 waddr, waddr 1773 drivers/media/dvb-frontends/drx39xyj/drxj.c rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); waddr 1836 drivers/media/dvb-frontends/drx39xyj/drxj.c u32 waddr, waddr 1852 drivers/media/dvb-frontends/drx39xyj/drxj.c rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, waddr 1874 drivers/media/dvb-frontends/drx39xyj/drxj.c u32 waddr, waddr 1883 drivers/media/dvb-frontends/drx39xyj/drxj.c waddr, waddr 1886 drivers/media/dvb-frontends/drx39xyj/drxj.c return drxj_dap_rm_write_reg16short(dev_addr, waddr, raddr, wdata, rdata); waddr 16 drivers/net/ethernet/altera/altera_sgdma.c dma_addr_t waddr, waddr 297 drivers/net/ethernet/altera/altera_sgdma.c dma_addr_t waddr, waddr 316 drivers/net/ethernet/altera/altera_sgdma.c csrwr32(lower_32_bits(waddr), desc, sgdma_descroffs(waddr)); waddr 13 drivers/net/ethernet/altera/altera_sgdmahw.h u32 waddr; waddr 2118 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c u32 fl_addr, waddr, raddr; waddr 2132 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c waddr = fl_addr & 0xFFFF0000; waddr 2133 drivers/net/ethernet/qlogic/netxen/netxen_nic_hw.c NX_WR_DUMP_REG(FLASH_ROM_WINDOW, adapter->ahw.pci_base0, waddr); waddr 1758 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 raddr, u32 waddr) waddr 1766 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); waddr 1771 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 raddr, u32 waddr, waddr 1790 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c qlcnic_83xx_wrt_reg_indirect(p_dev, waddr, value); waddr 251 drivers/nvmem/imx-ocotp.c u8 waddr; waddr 297 drivers/nvmem/imx-ocotp.c waddr = offset / priv->params->bank_address_words; waddr 305 drivers/nvmem/imx-ocotp.c waddr = offset / 4; waddr 310 drivers/nvmem/imx-ocotp.c ctrl |= waddr & IMX_OCOTP_BM_CTRL_ADDR; waddr 130 drivers/scsi/qla2xxx/qla_nx2.c uint32_t raddr, uint32_t waddr) waddr 135 drivers/scsi/qla2xxx/qla_nx2.c qla8044_wr_reg_indirect(vha, waddr, value); waddr 239 drivers/scsi/qla2xxx/qla_nx2.c uint32_t raddr, uint32_t waddr, struct qla8044_rmw *p_rmw_hdr) waddr 252 drivers/scsi/qla2xxx/qla_nx2.c qla8044_wr_reg_indirect(vha, waddr, value); waddr 874 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t raddr, uint32_t waddr) waddr 879 drivers/scsi/qla4xxx/ql4_83xx.c qla4_83xx_wr_reg_indirect(ha, waddr, value); waddr 894 drivers/scsi/qla4xxx/ql4_83xx.c uint32_t waddr, waddr 910 drivers/scsi/qla4xxx/ql4_83xx.c qla4_83xx_wr_reg_indirect(ha, waddr, value);