wa_ 87 drivers/gpu/drm/i915/gt/intel_workarounds.c struct i915_wa *wa_; wa_ 115 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_ = &wal->list[mid]; wa_ 117 drivers/gpu/drm/i915/gt/intel_workarounds.c if ((wa->mask & ~wa_->mask) == 0) { wa_ 119 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa_->reg), wa_ 120 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->mask, wa_->val); wa_ 122 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->val &= ~wa->mask; wa_ 126 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->val |= wa->val; wa_ 127 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->mask |= wa->mask; wa_ 128 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_->read |= wa->read; wa_ 134 drivers/gpu/drm/i915/gt/intel_workarounds.c wa_ = &wal->list[wal->count++]; wa_ 135 drivers/gpu/drm/i915/gt/intel_workarounds.c *wa_ = *wa; wa_ 137 drivers/gpu/drm/i915/gt/intel_workarounds.c while (wa_-- > wal->list) { wa_ 138 drivers/gpu/drm/i915/gt/intel_workarounds.c GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == wa_ 139 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa_[1].reg)); wa_ 140 drivers/gpu/drm/i915/gt/intel_workarounds.c if (i915_mmio_reg_offset(wa_[1].reg) > wa_ 141 drivers/gpu/drm/i915/gt/intel_workarounds.c i915_mmio_reg_offset(wa_[0].reg)) wa_ 144 drivers/gpu/drm/i915/gt/intel_workarounds.c swap(wa_[1], wa_[0]);