vupdate_width     437 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	input->dest.vupdate_width = pipe->pipe_dlg_param.vupdate_width;
vupdate_width    1181 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 			pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
vupdate_width    1222 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 						hsplit_pipe->pipe_dlg_param.vupdate_width = v->v_update_width_pix[input_idx];
vupdate_width    1958 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.c 	int vupdate_width,
vupdate_width     262 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator.h 	int vupdate_width,
vupdate_width     441 drivers/gpu/drm/amd/display/dc/dce110/dce110_timing_generator_v.c 	int vupdate_width,
vupdate_width     742 drivers/gpu/drm/amd/display/dc/dce120/dce120_timing_generator.c 	int vupdate_width,
vupdate_width     113 drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c 	int vupdate_width,
vupdate_width     131 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 	if ((pipe_dest->vstartup_start - 2*(pipe_dest->vready_offset+pipe_dest->vupdate_width
vupdate_width     768 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			pipe_ctx->pipe_dlg_param.vupdate_width,
vupdate_width    2510 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				pipe_ctx->pipe_dlg_param.vupdate_width);
vupdate_width      65 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 		int vupdate_width)
vupdate_width      72 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	optc1->vupdate_width = vupdate_width;
vupdate_width      84 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			VUPDATE_WIDTH, optc1->vupdate_width);
vupdate_width     145 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	int vupdate_width,
vupdate_width     165 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 	optc1->vupdate_width = vupdate_width;
vupdate_width     273 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c 			vupdate_width);
vupdate_width     519 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	int vupdate_width;
vupdate_width     564 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 	int vupdate_width,
vupdate_width     584 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h 		int vupdate_width);
vupdate_width     182 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 	if ((pipe_dest->vstartup_start - (pipe_dest->vready_offset+pipe_dest->vupdate_width
vupdate_width     574 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 			pipe_ctx->pipe_dlg_param.vupdate_width,
vupdate_width    1044 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 				pipe_ctx->pipe_dlg_param.vupdate_width);
vupdate_width    1336 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 					pipe_ctx->pipe_dlg_param.vupdate_width);
vupdate_width    2772 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			dst->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
vupdate_width    2787 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 						dst_j->vupdate_width = context->bw_ctx.dml.vba.VUpdateWidthPix[pipe_idx_unsplit];
vupdate_width     847 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	unsigned int vupdate_width;
vupdate_width    1001 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	vupdate_width = dst->vupdate_width;
vupdate_width    1027 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
vupdate_width    1034 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
vupdate_width     847 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	unsigned int vupdate_width;
vupdate_width    1001 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	vupdate_width = dst->vupdate_width;
vupdate_width    1027 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
vupdate_width    1034 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
vupdate_width     894 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	unsigned int vupdate_width;
vupdate_width    1041 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	vupdate_width = dst->vupdate_width;
vupdate_width    1067 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
vupdate_width    1074 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 				- (double) (vready_offset + vupdate_width + vupdate_offset) / htotal
vupdate_width     318 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int vupdate_width;
vupdate_width    1044 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	unsigned int vupdate_width;
vupdate_width    1226 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	vupdate_width = e2e_pipe_param.pipe.dest.vupdate_width;
vupdate_width    1296 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	line_setup = (double) (vupdate_offset + vupdate_width + vready_offset) / (double) htotal;
vupdate_width    1322 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	DTRACE("DLG: %s: vupdate_width      = %d", __func__, vupdate_width);
vupdate_width     144 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 							int vupdate_width,
vupdate_width     225 drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h 			int vupdate_width);