vsync_source      666 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0;
vsync_source      668 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c 			vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO;
vsync_source      174 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 		reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx];
vsync_source      178 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 	if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 &&
vsync_source      179 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 			cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) {
vsync_source      180 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c 		switch (cfg->vsync_source) {
vsync_source       68 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h 	u32 vsync_source;