vsync_pulse_width 2298 drivers/gpu/drm/drm_edid.c 	unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf);
vsync_pulse_width 2313 drivers/gpu/drm/drm_edid.c 	if (!hsync_pulse_width || !vsync_pulse_width) {
vsync_pulse_width 2343 drivers/gpu/drm/drm_edid.c 	mode->vsync_end = mode->vsync_start + vsync_pulse_width;
vsync_pulse_width  163 drivers/gpu/drm/gma500/intel_bios.c 		dvo_timing->vsync_pulse_width;
vsync_pulse_width  303 drivers/gpu/drm/gma500/intel_bios.h 	u8 vsync_pulse_width:4;
vsync_pulse_width   79 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	timing->vsync_pulse_width = mode->vsync_end - mode->vsync_start;
vsync_pulse_width  119 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	    timing->vsync_pulse_width;
vsync_pulse_width  144 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 	    timing->v_back_porch + timing->vsync_pulse_width;
vsync_pulse_width  168 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c 		timing->vsync_pulse_width);
vsync_pulse_width  100 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	vsync_period = p->vsync_pulse_width + p->v_back_porch + p->height +
vsync_pulse_width  103 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 	display_v_start = ((p->vsync_pulse_width + p->v_back_porch) *
vsync_pulse_width  172 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c 			p->vsync_pulse_width * hsync_period);
vsync_pulse_width   27 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h 	u32 vsync_pulse_width;